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jt2
基于FPGA的交通灯代码,VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)
- 2013-10-26 13:30:26下载
- 积分:1
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视频测试图形发生器
应用背景关键技术Altera FPGA ;CIII,Cyclone III implemented.16灰度320x240流视频信号发生器。
- 2022-03-05 02:38:57下载
- 积分:1
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signal
能产生正弦波、三角波、方波和e指数衰减的扫频波,且相关参数可调(Can produce sine wave, triangle wave, square wave, and e exponential decay wave sweep and adjustable parameters)
- 2014-05-13 15:15:12下载
- 积分:1
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4jieshuzilboqi
四阶数字滤波器 用不同的算法设计数字滤波器,并且有详细的是用方法(Fourth-order digital filter design with a different digital filter algorithms and a detailed method is)
- 2011-04-25 18:18:16下载
- 积分:1
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My_First_fpga
基于芯片5CSEBA6U2317,实现按键控制LED灯闪的速度的Verilog实现。(Realize the Verilog realization of the flow lamp.)
- 2018-05-03 09:58:41下载
- 积分:1
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pcf8563
pcf8563,在quartusII下VERILOG编写的数字时钟程序,8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)
- 2013-12-24 21:46:21下载
- 积分:1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分:1
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uart(可综合)
说明: 【实例简介】用Verilog实现uart串口协议,波特率可选9600、19200、38400、115200。8位数据为,1位校验位,1位停止位。
【实例截图】
【核心代码】核心代码包括TX,RX,Baud,FIFO([example introduction] UART serial port protocol is implemented with Verilog, and the baud rate can be 9600, 19200, 38400, 115200. 8-bit data, 1 bit check bit, 1 stop bit.
[example screenshot]
[core code] the core code includes TX, Rx, baud and FIFO)
- 2020-12-08 16:00:16下载
- 积分:1
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Traffic_RYG
说明: 交通灯的控制,分主干道和从路交通灯,主路优先,正常情况下,绿灯60s,红灯30S,黄灯5S(Traffic light control)
- 2020-06-21 06:40:02下载
- 积分:1
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微型 sd 卡 interface(sdmode)
本代码实现了sd卡接口驱动功能,实现了在sdmode下50Mbps的读写速率,也可以通过添加额外的命令来实现100Mbps的速写速率,而文件系统的实现可以在本接口的基础上来轻松完成,从而实现针对你的应用所需要的功能,本代码非常易读,大家可以轻松看懂!
- 2022-10-23 06:50:04下载
- 积分:1