linux环境下基于qt的mplayer视频播放器

avrusb源码，好--Source code for avrusb.

本程序为M190微型打印机的程序,采用C语言和汇编混合编写,已经经过调试并在应用中-procedures for the M190 Micro Printer procedures, and use of C language compilation mixed preparation, and after debugging applications

应用背景Abstract—Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive softcore for many-core research with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented

mega128控制单总线协议温度传感器18b20-mega128 control agreements single bus temperature sensor 18b20

嵌入式词汇大全,关于嵌入式开发的词汇手册-embedded vocabulary Daquan, on the Embedded Development Handbook Glossary

基于KL25定时器PWM输出可调脉冲。该评估板采用的主MCU型号为MKL25Z128VLK4，它的最大运行频率可达48MHz，集成了128KB的Flash、16KB RAM、一个全速USB控制器、以及一系列模拟和数字接口。MCU所有的功能管脚都引出，并配置有相应的外设。评估板功能丰富，结构简单，方便快速上手与学习Kinetis和ARM Cortex-M0+。

cs8900网络驱动-cs8900 Network Driver

利用stm8单片机编写的关于超声波模块的程序，包含超声波模块的程序  以及12864屏幕的程序，用以实时显示所测的距离  十分的准确  如有问题可以联系我  会细心解答

1602液晶显示程序+1302温度测量+18b20显示时间(C语言)-1602 LCD procedures+ 1302 temperature measurement+ 18b20 display time (C language)

FPGA DE2开发板  实验2第一部分VHDL硬件语言练习源码 Part II You are to design a circuit that converts a four-bit binary number V = v3v2v1v0 into its two-digit decimal equivalent D = d1d0. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit by creating a VHDL entity which includes the comparator, multiplexers, and circuit A (d