ahb_slave 在先进的单片机总线体系结构

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

说明：  demo6 蜂鸣器实验 蜂鸣器演奏音乐(demo6 buzzer buzzer experiment playing music)

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对4x4键盘的输入控制，并显示在一个8段式数码管上。(The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.)

SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)

它是一种算法，它是用来在超大规模集成电路的乘法2

用verilog实现endat2_1驱动,并用signalTap捕捉信号。(Using verilog achieve endat2_1 drive and use signalTap capture signal.)

说明：  通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

我以altera公司的 FPGA，型号是DE2 系列 软件的版本是quartusii  9.0  程序实现了2,4,6,8，分频，

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)