-
altera_fft
verilog实际例子,非常适合初学者学习(verilog practical examples, very suitable for beginners to learn)
- 2020-12-06 16:49:22下载
- 积分:1
-
squareLoop
利用平方环法提取同步载波的FPGA实现的仿真(FPGA implementation of synchronous carrier extraction using square loop method)
- 2021-01-11 17:18:49下载
- 积分:1
-
flash
本程序是fpga控制flash的读写程序,包括了程序和仿真时的测试文件(fpga flash)
- 2013-07-21 14:47:36下载
- 积分:1
-
Verilog HDL 4bit_processor
RTL码由控制、alu、寄存器、keych模块等组成。。。
- 2023-04-12 17:35:03下载
- 积分:1
-
彩灯控制、数码管循环显示1~8、1010序列检测器
verilog实现彩灯控制、数码管循环显示1~8、1010序列检测器,代码在文件里
- 2022-03-19 02:07:26下载
- 积分:1
-
fir48
48阶FIR滤波器的verilog,包含测试文件(48-order FIR filter verilog, including test paper)
- 2021-04-14 19:58:55下载
- 积分:1
-
中值滤波verilog
中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog
- 2023-03-28 00:30:04下载
- 积分:1
-
VGAzifuxianshi
用VERILOG编写的VGA字符显示,可以在电脑屏幕上显示字符,已通过测试(Prepared with the VERILOG VGA character display, can display characters on a computer screen, has been tested)
- 2011-01-01 14:50:47下载
- 积分:1
-
1 bit full adder
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:40:20 01/09/2019
// Design Name:
// Module Name: fulladder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fulladder(
input a, b, cin,
output s, cout
);
assign s=a^b^cin;
assign cout= a&b| b&cin | cin&a;
endmodule
- 2022-02-12 01:48:54下载
- 积分:1
-
Ffpga-jpegP
基于FPGA的JPEG图像压压缩,实现JPEG图像的实时压缩
(Real-time compression pressure compressed FPGA-based JPEG images, JPEG images)
- 2012-08-23 22:11:39下载
- 积分:1