ahb_slave 在先进的单片机总线体系结构

基于DE2_70平台，编写nios软核c代码，控制流水灯，硬件实现验证通过，适合入门(Based DE2_70 platform, written nios soft core c code, control water lights, verified by hardware implementation, suitable for entry)

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

此功能需要写在你的模块结束或在您的测试台，显示你的定点实数。

通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)

进阶实验之SRAM测试，由verilog编写，可直接对sram进行存写(Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write)

基于FPGA的PAL_VGA转换器的实现.pdf(FPGA-based PAL_VGA converter implementation)

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)