GAL16V8反汇编源程序JED2ABEL.C 把jec汇编成abel文件

说明：  stepper motor module on spartan 6 and 24MHz clock fequency

ＦＰＧＡ设计中的一些经典例子对学习ＦＰＧＡ的人会有帮助-FPGA design of some of the classic examples of people learning FPGA would be helpful

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)

一些非常有用的程序，均经过调试，让大家一块共享。(Some very useful procedure, have been testing, so that everyone shared one.)

说明：  通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

说明：  CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。(CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.)

含移动储能的分布式电能优化调度，模型的处理与改进(Processing and improvement of distributed power optimization scheduling with mobile energy storage)

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

fifo程序代码，程序编写，测试仿真图形，方便，比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)