GAL16V8反汇编源程序JED2ABEL.C 把jec汇编成abel文件

用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication

1．初始状态为4个方向的红灯全亮，时间1秒。 2．东、西方向绿灯亮，南、北方向红灯亮。东、西方向通车，时间30秒。 3．东、西方向黄灯闪烁，南、北方向红灯亮。时间2秒。 4．东、西方向红灯亮，南、北方向绿灯亮。南、北方向通车，时间15秒。 5．东、西方向红灯亮，南、北方向黄灯闪烁。时间2秒。 6．返回2，继续运行。 -1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.

用FPGA实现SDRAM的操作，具体操作见内部说明文件-FPGA SDRAM with the operation of the specific see internal note

MATLAB Filter Design HDL Coder Simunlink HDL Coder Xilinx ISE Webpack

FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过-Stepper motor stepper motor position location system system block symbol file location stepper motor system Verilog HDL program design has been compiled through

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)

用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources.

这是一个基本的ARM7_Core 有基本功能 但不是太完善-This is a basic ARM7_Core has the basic functions, but not too perfect