实现串口传输代码

decoder 2-4 digital core

本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。 (In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)

floating point alignment

FPGA AD数据采集模块，实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)

MAX2839寄存器配置  spi程序                                                                                                                                                                  &nbs

语言代码编码中用于添加 2 xilinx 浮点数...... 和此编码中使用的技术是 piplining......

An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.

说明：  用matlab将图片转成灰度图TXT，再通过verilog将数据导入FPGA中，采用高斯滤波算法来处理，再将处理后的图片数据导出到TXT中。(The image is transformed into gray-scale image TXT by MATLAB, and then the data is imported into FPGA by Verilog, processed by Gauss filter algorithm, and then the processed image data is exported to TXT.)

使用Verilog编写代码，实现集成芯片MT89L80的功能，代码配置ram后可以直接使用，完成256x256个时隙交换，其中主要模块包括接收模块、发送模块、cpu接口模块，寄存器配置模块，接续寄存器模块等。

hdb3 using language VHDL(Indoor using VHDL language)