实现串口传输代码

说明：  内部含3个模块，使用DDS产生200k与500k的正弦波，两者相加后过数字低通滤波（通带0-200k，阻带400k以上），并将波形输出，实测FFT分析中看不到500k分量。其中数字滤波器采用MATLAB设计（FIR+等波纹，阻带衰减-80dB）(There are three modules in the system. DDS is used to generate 200K and 500K sine waves. After adding the two modules, the digital low-pass filter (passband 0-200k, stopband above 400k) is used, and the waveform is output. 500K component can not be seen in the actual FFT analysis. The digital filter is designed by MATLAB (FIR + equal ripple, stopband attenuation - 80dB))

VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

用Verilog实现汉明码编码，经测试可正确使用，代码简洁(Verilog with Hamming code encoding, the test can be used correctly, the code is simple)

HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)

一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)

adder 18b trong chuong trinh verilog

基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

这是完整的verilog控制ds18b20的程序，已在板子上运行了很长时间，很稳定，200M以下时钟皆可稳定运行（我是按照200M来设计的），上传的文件格式为.dat（在此不说明原因），下载后修改后缀名为.v即可使用，我也是为了积分才上传的，绝对可信，