ad9740控制程序

代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少(Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less)

EP2C35A实验箱基于NIOSII的串行AD_DA编程(EP2C35A experimental box based NIOSII the serial AD_DA programming)

数字钟(Digital clock)

基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)

ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码(ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code)

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

verilog语言编写的farrow滤波器的实现过程，供大家参考，谢谢。(Verilog language Farrow filter implementation process for your reference)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

应用背景使用Verilog编写的sdram猝发读写程序，经测试可使用，猝发读写长度为8,16位的sdram接口。可应用与图像接收和处理平台。关键技术采用猝发的方式读写sdram，使得sdram的频率大大提高，完全可以应用于图像等处理平台中。测试过完全没有问题。

说明：  FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)