使用fpga基于积分分离的pid算法进行温控的程序

与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)

本压缩包，包换一个用verilog语言实现的huffman编码源程序，同时给出了众多论文和基础知识的文档资料，一应俱全。(The compression package, shifting one using huffman coding verilog language source code, and gives basic knowledge of many papers and documentation, everything.)

在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)

This source is used to control 7 segments on FPGA boad

基于CS的一维距离像（HRRP）及FFT成像对比(CS-based HRRP and FFT HRRP)

改VHDL代码可以实现超声波测距的功能，其精确度达到US级，可以用七段数码管显示其数值(sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging )

描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)

Verilog HDL 读取EEPROM项目的详细构建(Verilog HDL EEPROM read the detailed construction)

此文件描述的 verilog booth 型乘法器的代码。源代码是模拟和验证效果会更好