FPGA数码管时钟显示

简单的以太网例程,verilog语言,vivado环境

DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器(DDS_AD9854_for FPGA, verilog source code, signal generator.)

约束所有时钟（包括你的设计中特有的时钟）对准确的时序分析结果而言是必不可少的。Quartus II TimeQuest Timing Analyzer为各种各样的时钟配置和典型时钟提供许多SDC命令。(Constraining all clocks, including the clocks unique to your design, is essential for accurate timing analysis results. The Quartus II TimeQuest Timing Analyzer provides many SDC commands for a variety of clock configurations and typical clocks.)

基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)

Construction and Experimental Evaluations of User-Centered Power

在FPGA开发平台上，通过按键控制一个弹球小游戏。输出VGA显示信号输送到显示器上显示(On the FPGA development platform button control of a pinball game. VGA output signal is supplied to the display displayed on the display)

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)

vivado工程下的Verilog语言的CRC_16,并行输入任意字节长度，均可求出来，数据的校验码，代码给的是512个字节宽度的数据源，长度可以自行修改，亲测实际工程~~~

利用VHDL编写的电子琴发生器，以简单的演奏电路论文(Electronic organ prepared using VHDL generator to perform a simple circuit Papers)