Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, en...

使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

FPGA中实现的硬件UDP 协议 FPGA中实现的硬件UDP 协议

AD706在Sparten6使用的FPGA代码，测试通过(AD706 FPGA Code In Sparten6)

基于FPGA的1553B总线编码解码器的设计-1553B Bus FPGA-based codec design

vhdl经典源代码――vga控制，入门者必须掌握-vhdl classical source code-- vga control, beginners must master

UART串口的verilog源代码，完全正确...........(UART serial Verilog source code, completely correct ...........)

cic_dec_8_three CIC 文件的ＶＨＤＬ-cic_dec_8_threeCIC documents VHDL

这一计划表明它是如何在如此逻辑门是门NAND，什么它NAND它是结合两个闸门之一，并没有。

用VHDL实现60秒倒计时的功能 倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)