Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, en...

基于分裂基的蝶型FFT，用C实现，经过测试，没有错误，可以直接拿去使用。(Based on the division of FFT butterfly type, use C implementation, tested, no error, can directly use. )

2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)

FPGA设计全流程－软件综合使用、 -FPGA design of the whole process- the integrated use of software, FPGA design of the whole process- the integrated use of software,

DE2将连接到LCD布局上，为Terasic off技术公司附上系统代码

说明：  将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

stepper motor module on spartan 6 and 24MHz clock fequency

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

这是我自己写的4位并转串ISE代码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!

通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)