AMBA 3 协议

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

在PVI接收16位并行数字流（视频），其次是一个时钟信号（英尺= 29兆赫），小写字母

eda的入门学习课件，老师不错，内容页挺好的(eda learning files)

LDPC编码的Verilog HDL程序源代码，包括仿真数据等，内容比较全，用quartusII仿真的。

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

NAND型闪存接口程序 里面包含了datasheet以及测试程序 (NAND flash memory interface program)

USB转RS232RSTTLRS485FT232+SP213串口的原理图AD画的(USB to RS232RSTTLRS485FT232+SP213 serial port schematic AD drawing)

本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。(The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Chapter VII of the future design examples, not only examples of Verilog-HDL, but also attached, including VB, VC++ source code, etc., and even DLL generation methods explained in detail.)

基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)

用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。(It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.)