AMBA 3 协议

huffman transform in vhdl language

verilog编写的数字信号发生器NCO用CORDIC方法实现产生sin cos信号，流水线结构，简单实用。(verilog prepared by the digital signal generator NCO using CORDIC method implementation generate sin cos signal, pipelined architecture, simple and practical。)

我必须做智商演示项目。我不知道写代码verilog.so版本请提供matlab和verilog在fpga中的编码实施iq解调器由以下模块组成：射频调制信号、混频器、低通过滤.it包含同相分量、正交分量。

介绍 verilog 语言，用于实现包括乘法计算两个 32 位数字。在码，我输入我的 CWID 和 41411 来验证功能。您可以更改要计算不同的值的十六进制文件。体系结构 ︰ 携带-波纹 + 进位跳跃。

6层电梯设计，采用vhdl编写，能够实验电梯功能(6-story elevator design, using vhdl prepared, able to lift function experiments)

说明：  biss协议源码交流 verilog hdl源码，测试可用(Biss protocol ,achieved by verilog HDL,can be verify using modelsim or other simtools.)

usb3.0 物理层仿真，verilog编程(Start the physical simulation)

verilog编写的uart发送模块，起始位，数据位，可选择的奇偶校验位，停止位。仿真可用

Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display

说明：  AD9250是一款双通道14位ADC，最高采样速率250 MSPS，JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)