查找序列序列中两个相邻1之间的最大间隔

FIFO 是缓冲区的一种特殊类型。名称 FIFO 站第一的先进先出和入缓冲区中，第一次写入的数据第一次出来它的手段。每个内存的数据字所写的第一次也出来第一次当读取内存是先进先出。先进先出的三个种类：移位寄存器 — — 与存储的数据字的恒定数目和因而，读和写操作之间的必要同步 FIFO 因为必须读取数据字，每次一种书面独占读取/写入 FIFO — — 具有可变数量的存储的数据字，和由于内部结构，读和写操作之间的必要同步先进先出并发读/写 FIFO — — 数量可变的存储的数据的言行可能读和写操作之间的异步 FIFO

实现I2C协议下EEPROM存储的数据读写控制(Under I2C protocol to achieve read and write data stored in EEPROM control)

floating point alignment

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)

使用Verilog语言编程，在Quartus ii 上实现的误码检测装置，并通过单片机将误码结果显示在LCD上。本代码具有一定的工程实践价值。(Using the Verilog language programming, implemented on the Quartus ii error detection device, and the result of errors by the microcontroller on the LCD display. The code has some value engineering practice.)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command)

说明：  该设计使用8个AXI视频直接存储器访问（AXI VDMA）引擎同时移动16个流（8个传输视频流和8个接收视频流），每个流以1920 x 1080像素格式以60赫兹刷新率移动，每个像素24个数据位。此设计还具有额外的视频等效AXI流量，该流量由为1080p视频模式配置的四个LogiCORE AXI流量发生器（ATG）核心生成。ATG核心根据其配置生成连续的AXI流量。在本设计中，ATG被配置成以1080p模式生成AXI4视频流量。这使得系统吞吐量需求达到DDR的80%左右带宽。每个AXI VDMA由LogiCORE IP测试模式生成器（AXI TPG）核心驱动。AXI VDMA配置为在自由运行模式下运行。每个AXI VDMA读取的数据被发送到能够将多个视频流多路复用或叠加到单个输出视频流的通用视频屏幕显示（AXI OSD）核心。AXI OSD核心的输出驱动板载高清媒体接口（HDMI技术）视频显示接口通过RGB到YCrCb颜色空间转换器核心和逻辑核心IP色度重采集器核心。LogiCore视频定时控制器（AXI VTC）生成所需的定时信号。(The design uses eight AXI video direct memory access (AXI VDMA) engines to simultaneously move 16 streams (eight transmit video streams and eight receive video streams), each in 1920 x 1080 pixel format at 60 Hz refresh rate, and 24 data bits per pixel. This design also has additional video equivalent AXI traffic generated from four LogiCORE AXI Traffic Generator(ATG) cores configured for 1080p video mode. The ATG core generates continuous AXI traffic based on its configuration. In this design, ATG is configured to generate AXI4 video traffic in 1080p mode. This pushes the system throughput requirement to approximately 80% of DDR bandwidth. Each AXI VDMA is driven from a LogiCORE IP Test Pattern Generator (AXI TPG)core. AXI VDMA is configured to operate in free running mode. Data read by each AXI VDMA is sent to a common Video On-Screen Display (AXI OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream.)

实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)

题目来源于学校的课题系统硬件综合设计，代码中有单周期CPU设计，多周期流水线CPU设计，使用的是Verilog语言，多周期的是基于MIPS架构。