PCI Verilog RTL代码、文档

Quartus II 7.2最完美的license破解器!(Quartus II 7.2 FULL and perfect License!)

lap of altera . it s basic about verilog

SDRAM的相关资料！包括三星的资料。有大量的论文，有原理图，有仿真程序等。

给大家上传一本非常好的关于verilog-hdl的电子书，实用，易懂，易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. 

CSCC标准下的RS(255,223)码的译码器设计，采用verilog语言编程实现，在软件QUARTUS II 9.0环境下仿真通过，并在CYCLONE IV系列开发板调试通过。

在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)

说明：  I2C MASTER DESIGNED by Verilog

通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)

dual port ram control (dual port ram control dual port ram control dual port ram control)