APB 2.0 Master

本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。 (In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)

SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

说明：  Ovo sto saljem je tutorijal 7 sa vhdlom

用Verilog编写的以太网控制器，可以使用，里面是全部verilog源码(Ethernet controller based on Verilog, can be used directly, all verilog files)

说明：  ip core of the transceiver gtx

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

verilogPWM波的设计，属于数字电子技术实验入门的资料

说明：  DAC3283 寄存器初始化，SPI驱动(Dac3283 register initialization, SPI drive)

自动计算fir滤波器系数的工具，不妨一试(Automatic calculation of filter coefficients fir tools, try)