用于sopc builder添加组件用的ps/2 键盘 ipcore

说明：  matlab code for JTAG cable checking

说明：  Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

Kluwer academic the verilog hardware description language fith edition

Conduct a digital system ( electronic lock ) using hierarchic methodology . An electronic lock is a device that allows access or opening of a system , as long as the key or combination to enter match with which it is predefined in said lock .

这是基于MATLAB编程实现自适应滤波器，并在XILINX的FPGA上硬件可实现的模型文件(This is based on the MATLAB programming adaptive filter, and the XILINX' s FPGA hardware can be a model document)

该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。(This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.)

UDP / IP上的Spartan3E以太网通信通过斯巴达3E发送UDP数据包到/从我的电脑。

用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)