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基于FPGA的增量式光电编码器计数电路设计,文章含有Verileg HDL代码.-FPGA-based incremental photoelectric encoder count circuit design, the article contains Verileg HDL code.

快捷实现数据复制和磁盘运行,window linux-Realize fast data replication and disk run, window linux

能够进行矩阵运算，可以自己下载添加上说明就可以达成课程设计报告额-To carry out matrix operations, you can download the add on your description of the report of the amount of curriculum design can be reached

基于专用运动控制芯片的开放式数控系统研究 -Special motion control chip based on Open CNC System

一种分布式视频点播系统的设计与实现 硕士学位论文-A Distributed VOD System Design and Implementation of a master

关于lpc2214远程IAP升级程序的方法-about update your program by IAP

VHDL 基于FPGA 和VGA 接口的应用设计-vhdl

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This document related to CBIR - Content Based Image Retreival System. Average RGB concept is used.-This document related to CBIR- Content Based Image Retreival System. Average RGB concept is used.

多功能数字钟设计 一、设计任务： （一）主体功能 用HDL设计一个多功能数字钟，包含以下主要功能： 1.计时及校时，时间可以24小时制或12小时制显示 2.日历：显示年月日星期，及设定设定功能 3.跑表：启动/停止/保持显示/清除 4.闹钟：设定闹钟时间，整点提示 -multifunctional design of a digital clock, design tasks : (1) the main function of HDL design with a multi-function digital clock, includes the following main functions : 1. metering and school, time can be 24 hours or 12 two-hour show. Calendar : Displays date weeks, Setting function and 3. stopwatch : start/stop/maintain Display/4 clearance. alarm clocks : Set an alarm time. suggested the whole point