基于FPGA数字频率计

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Digital Design and Modeling with VHDL and Synthesis

- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)

VHDL code of a counter Code VHDL d un compteur

编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。-Implementation cycle of the compiler generated code, respectively, using FOR Cycle one of the key element of the set.

Altera DE2 开发板试验2 第1部分VHDL答案(Altera DE2 Lab2 part1 VHDL answer)

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

这是一个基于可编程逻辑器件的程序，用来实现自动转换量程频率计控制器，该程序在可以再仿真器上仿真实现-This is a programmable logic device based on the procedures used to automatically convert the frequency range of the controller, the program can be in the simulation simulator

USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code

最近交互式电源技术，软交换、同步整流、频率固定(Alternating expressions Power technology recently、Softswitch, synchronous rectification, fixed frequency)