基于FPGA数字频率计

FPGA UART 发送端程序 verilog语言编写 9600波特率 实用(UART transmit side program verilog language 9600 baud)

四选一编程语言，可以自动生成四选一器件。-First elected four programming languages, you can automatically generate a four selected devices.

基于BCD码的十进制ALU设计，可实现加减乘除的功能(BCD to decimal ALU based design can achieve the arithmetic function)

AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)

I2C的实现，可以扩展进而控制有关I2C的器件达到操作员的控制目的。(I2C implementations, can be extended further having control of the I2C device operator control purposes.)

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest

说明：  汉明编码和解码的硬件描述语言（verilog），其被编解码的数据为M序列。 建议运行软件为Quartus.(failed to translate)

实现FPGA与PC通信的USB2.0接口,采用verilog语言实现(Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve)

ise平台模拟UART，并与PC机实现收发（+1）(ISE platform simulation UART and transceiver.)