基于FPGA数字频率计

Fonts for LCD 162x64 (6x8)

通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)

I am in need of some codes of HDL

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

说明：  xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)

说明：  学习fpga的工具signaltap软件使用说明书，好工具(Learn the instruction manual of signaltap software, a good tool)

verilog例子资源，对于初学者很有帮助。-verilog examples of resources are very useful for beginners.

用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.

spi-slave通信的vhdl实现及其仿真(VHDL implementation of spi-slave communication)

16b20b encoder and decoder