基于FPGA数字频率计

基本功能的cpu，自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)

The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below:   tl   - HDL design files   sim   - simulation files   synth - Synthesis related files   par   - Place/Route related files 以及DDR SDRAM控制器设置.pdf文件

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

This is code of UVM CALLBACK function.

Interface for ADS8361 TI ADC IP Core for ALTERA NIOS2

design cpu 16 bits by verilog HDL.

说明：  自己设计的一个其人投票系统，对于VHDL初学者可以参考下(One of their own design their human voting system, for VHDL beginners can refer to the following)

用Verilog编写ad_9866的相应程序，在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)

该部分的主要功能是完成基于FPGA的polar码SC译码。(The main function of this part is to complete the FPGA-based polar code SC decoding.)

verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be