scramble

UART包括发射机和接收机。发送器本质上是一个加载数据的特殊移位寄存器；

说明：  本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。(I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book )

说明：  PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)

SD卡读写源代码.用Verilog编写.很不错.值得借鉴.特别对SD卡开发的人员!(SD card reader-writer source code. Prepared to use Verilog. Is pretty good. Be used for reference. In particular, the development of personnel SD card!)

C语言写得FIR滤波器代码，简单实用，是学习滤波器设计的好材料，附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design )

说明：  一个编码解码系统，其中包含一个信号发生器（用查找表方式实现）、一个m序列生成器（用来编码和解码用）、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)

基于DB8小波变换的verilog代码设计，支持Avalon总线(Verilog DB8 Wavelet Transform Based on code design, support Avalon bus)

This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan-6 FPGAs.

基于verilog的SD卡读取图片显示例程的实验 基于verilog的SD卡读取图片显示例程的实验 基于verilog的SD卡读取图片显示例程的实验 基于verilog的SD卡读取图片显示例程的实验 基于verilog的SD卡读取图片显示例程的实验