sumador 4 位空格 de 2 numeros hexadecimales con resultado en 十进制 en 联合国显示德 7 segmentos 语言

Verilog 写的HDMI接口源程序及说明文档(HDMI interface verilog code and specificaiton paper)

this project is about FIR FIlter By VHdl codes in the ISE.

很简单的一个分频器设计，不过不光是分频器，里面还加入了一些其他功能，e.g.七段译码管，138译码器等元素

emWin 在LPC2478上实现LCD的高性能显示(emWin to achieve high-performance LCD display in the LPC2478)

实现基于matlab的QMFB的完全重建，是一篇经过仿真且经过测试的正确的代码，可用价值比较高。(Based on matlab QMFB the completely rebuilt, is a through simulation and tested the correct code, can be relatively high value.)

自己用verilog编写的urisc程序，调试成功，压缩包里有仿真图像，值得学习参考。(Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.)

DESCRIPTION OF FULL ADDER

CS5460校准程序，控制器为C8051F310，SPI通信协议，可以作为电表芯片示例(CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample)

对SPI接口的verilog编程，SPI is a simple interface that allows one chip to communicate with one or more other chips.   

VHDL code comparator