sumador 4 位空格 de 2 numeros hexadecimales con resultado en 十进制 en 联合国显示德 7 segmentos 语言

实现FPGA与PC通信的USB2.0接口,采用verilog语言实现(Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve)

说明：  EDA软件VCS学习中用到的实际例子，都已经通过调试验证(Practical examples used in the learning of EDA software VCS have been verified by experiments.)

说明：  PIC单片机学习软件及其资料，入门到精通(PIC MCU learning software and its information, entry to proficiency)

说明：  用于FPGA中zynq的温度上报，通过逻辑方式。(It is used to report the temperature of zynq in FPGA by logic)

BCD to 7 segments display decoder

emmc协议的实现代码，包含了SD协议，usb实现协议(The implementation code of EMMC protocol)

圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)

说明：  完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)

Verilog code for RS-(255,239) encoder.

SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)