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QPSK
用VHDL语言实现QPSK调制功能和解调功能,(Using VHDL language features QPSK modulation and demodulation functions,)
- 2021-04-26 15:28:46下载
- 积分:1
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clk_generator
时钟分频代码,PWM产生 RTL 源代码。(clock divider,PWM generator RTL Source Code)
- 2013-08-18 09:29:42下载
- 积分:1
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svtb_ahb_sram
说明: 一款verilog设计的SRAM控制器,可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)
- 2020-06-30 13:40:02下载
- 积分:1
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divf_even
基于FPGA cyclone2的偶数分频模块,可实现自定义分频数(Based on FPGA cyclone2
even number of frequency divider module, custom frequency divider can be realized.)
- 2018-11-06 12:11:46下载
- 积分:1
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mu0
基于Xilinx Spartan6的
一个简单的CPU MU0
VHDL(Based on a simple CPU Xilinx Spartan6 of MU0 VHDL)
- 2020-12-07 08:29:22下载
- 积分:1
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FPGA控制LCD_Panel
本人上网下载下来并调试过的,完全实现NIOS 点亮LCD_Panel,附件是驱动部分。
- 2023-02-05 21:30:03下载
- 积分:1
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数字频率计
说明: 设计一简易数字频率计,其基本要求是:
1)测量频率范围0~999999Hz;
2)最大读数999999HZ,闸门信号的采样时间为1s;.
3)被测信号可以是正弦波、三角波和方波;
4)显示方式为6位十进制数显示;
5)具有超过量程报警功能。
5)输入信号最大幅值可扩展。
6)测量误差小于+-0.1%。
7)完成全部设计后,可使用EWB进行仿真,检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are:
1) The measuring frequency range is 0-999999 Hz.
2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s.
3) The measured signal can be sine wave, triangle wave and square wave.
4) The display mode is 6-bit decimal number display.
5) It has alarm function beyond range.
5) The maximum amplitude of input signal can be expanded.
6) The measurement error is less than +0.1%.
7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)
- 2019-06-20 12:47:51下载
- 积分:1
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zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形,但并没有使用ISE内部的FIR滤波器内核,该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分:1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言,支持VHDL和verilog 语言方便移植,如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分:1
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ds180_7Series_Overview
对赛灵思7系列的三种型号的FPGA进行了综述(xilinx 7 productin overview)
- 2012-06-13 15:04:23下载
- 积分:1