DDR2 SDRAM CONTROLER

一个交通灯设计,简单的实现，没有添加其他的显示管(Traffic Light System)

说明：  verilog讲义 卡内基梅陇大学verilog课程讲义-unlocked 卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)

基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)

用verilog编写的huffman解码程序(huffman decoder verilog)

The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).

说明：  实现fpga 读写flash 在k7上验证(Realization of FPGA read-write flash verification on K7)

Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )

UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在FPGA开发板设计中，UART用来与PC进行通信，包括数据通信，命令和控制信息的传输。实验之前我们先来了解一下Uart的通信协议和传输时序。

FPGA时钟显示程序，可以按照正常的时间，频率可调，数码管显示00-00-00，中间的-可改。只要采用嵌套的循环结构实现

中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)