DDR2 SDRAM CONTROLER

基于FIR滤波器的LMS自适应算法的FPGA实现,verilog语言(FIR filter based on LMS adaptive algorithm on FPGA, VHDL language)

uart接收模块 // 波特率：9600 // 数据位：8 // 停止位：1 // 校验位：0(UART receive module Baud rate: 9600 / / / data: 8 / / stop: 1 / / check digit: 0)

说明：  30 bus for atp design

This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing

32bit floating point addition

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

说明：  QUARTUS2 16.9 VHDL FPGA ENDAT2.2

用于检测信号上升沿，输出与时钟相关的正脉冲(Detect the rising edge of the signal)

Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法(Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide)

基于FPGA的电子密码锁设计-已在开发板上成功运行，通过老师检验。(FPGA based electronic password lock design- has been successfully developed on the development board, through the teacher inspection.)