网卡的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.

NOR FLASH CONTROLLER

用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!

说明：  DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good)

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)

基于BCD码的十进制ALU设计，可实现加减乘除的功能(BCD to decimal ALU based design can achieve the arithmetic function)

经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)

vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。(vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.)

here is a VHDL example

spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)

曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code