第五部分 按键检测例程

本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)

AD0832 AD转换程序，功能完全通过测试，备注非常详细，KEILC编程，通用性强(AD0832 AD converter, fully functional test, notes, very detailed, KEILC programming, versatility)

The aim of the ECG simulator is to produce the typical ECG waveforms of different leads and as many arrhythmias as possible. My ECG simulator is a matlab based simulator and is able to produce normal lead II ECG waveform.

timblogiw.c timberdale FPGA LogiWin Video In driver.

dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

一个基于FPGA用verilogHDL设计的bayer格式转RGB格式的模块，本人设计(a code used for bayer_3RGB_interpolation ,which based on FPGA by verilogHDL)

PCS和PMA都包含在OSI参考模型的物理层内。PCS和千兆媒体独立接口（GMII）彼此经由8位并行数据线和多个控制线进行通信。PCS负责编码传下来的GMII到10位码组每个字节。PCS还负责解码向上传递从PMA成八位位组中使用由上层10位码组。PCS还控制自动协商过程中，允许两个独立的千兆设备，建立其中一个链接他们都能够使用。

说明：  一个小寄存器堆，使用参数化编程，附有仿真代码，可直接在vivado（2018.2版本及以后）上运行(A small register heap, using parametric programming)

在本文设计的 32 位携带看超前进位加法器做.the 通过设计 8 4 位共轭亚油酸块降低复杂度。