the program have designed a PCM signal timing modules, including the CLK input,...

一个关于VERILOG与VHDL混合编程，混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)

说明：  5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

4X4 KEYPAD 的密码比较模块，可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6

Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1

UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列 UG C program，homework，student，study，first，hole，complex，many( UG C program，homework，student，study，first，hole，complex，many)

说明：  fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。(Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.)

说明：  FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)

基于FPGA的PAL_VGA转换器的实现.pdf(FPGA-based PAL_VGA converter implementation)

ADC TLC5510的测试程序，经过测试通过，十分简单好用-ADC TLC5510 test procedures, after the test is very simple and easy