verilog语言的fpga全数字锁相环ADPLL程序

一个简易数字钟程序，可以实现24小时精确计时、整点报时、时钟矫正、时钟复位等功能

xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中(xilinx FPGA design needs DDR2 files that can be applied to the actual design)

DCT and Idct with vhdl and verilog

说明：  反应力测试 利用图片的变换根据用户点击的反应时间判断(Reaction force measurement using the picture of the transformation reaction time based on user clicks judgment)

adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

这个是verilog下miller米勒编解码，小实验。直接运行即可，将时间轴拉大即可看到具体波形。

说明：  模拟交通灯 verilog CPLD EPM1270 源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)

VHDL book for reference

The description header can be found in signal_processing_library.h.

本书通过100个实例，详细介绍便件描述语言vHDL的各种语法现象及其在专用集成电路(AHc)设计蝴还中的使用方法。(the book through one hundred examples, it detailed description language vHDL pieces of the phenomenon and its various grammatical in ASIC (AHc) were also designed butterfly The usage.)