超前进位加法器

说明：  基于FPGA的任意波形发生器DDS,verilog编写，正常使用(Arbitrary waveform generator DDS based on FPGA)

4位的超前进位加法器，门级电路连接得到，verilog代码实现(4-bit look-ahead adder, gate-level circuit)

网络通信中的MII接口 通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用 同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)

华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)

用verilog实现64点，128点，256点的fft(64 points, 128 points, and 256 points FFT are implemented with Verilog)

基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)

是基于FPGA的5620的数模转换芯片底层的应用程序，希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)

MAX262是一款可程控滤波芯片,该是它的英文数据手册.(MAX262 is a programmable filter chip, which is its data sheet in English.)

16次迭代的CORDIC算法，精度很高，可应用于计算反正切值(16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent)

LCD1602显示源码，verilog编写，已在版上测试过！可输入字符串显示！！！！！！！！