firewall

IC的设计可以分为两个部分，分别为：前端设计（也称逻辑设计）和后端设计（也称物理设计），这两个部分并没有统一严格的界限，凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design related to process can be called back-end design.)

GPS 导航器TFT 驱动源程序。主CPU为ATmel的AT91sam9261（ARM926的内核）(TFT GPS navigation device driver source code. CPU for the AT91sam9261 ATmel (ARM926 the kernel))

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

此建业 2.0 解释建业桥的 i2c 接口的主设备和从设备操作。 — 建业先进的外围组件包括许多行业常用的接口 IP。以确保可以跨不同范围的 IC 进程迁移的高度可重用的外围设备和系统宏细胞。

本代码我们做的是“回环测试”，上微机首先通过串口通信发送数据到FPGA，FPGA接收到数据以后再将其发回给上位机，通过观察上位机的数据显示窗口，我们就能确定基于FPGA的串口数据手法是否正确。

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

VHDL code comparator

说明：  verilog 版本，Xilinx玩转USB3.0，LVDS接口(verilog version,Xilinxplay with USB3.0,LVDS)

代码用两种方法设计了一个基于多相滤波的内插器，低通滤波器采用128阶凯撒窗，内插倍数32，并且给定信号范围，验证了内插器的正确性，画出了内插前后信号的频谱。(The code design the interpolator based on polyphase filter using two methods.The low pass filter is 128 order Caesar window and interpolation multiple is 32.I give the range of the signal to verify the interpolator and plot the spectrum of the signal before and after the interpolator. )

DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)