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当前SOC是嵌入式系统设计的一大热点，本资料已ARM926EJS为基础，详细讲解了SOC的设计。-current SOC embedded system design is a hot topic, this information has been ARM926EJS basis, gave a detailed account of the SOC design.

This code is interfacing 4x3 keypad and 16x2 lcd to at89c52 micro controller and can be used in others as well. The design is done using proteus simulator

　　Windows CE是微软为嵌入式设备打造的操作系统，而嵌入式设备可谓多种多样，这就要求CE操作系统必须是可定制的，所以微软将Windows CE设计为模块化的操作系统。说简单点，我们可以把Windows CE想像成一盒积木，你可以用积木搭建出任何物体，但不一定要把所有的积木都用上-Microsoft Windows CE for embedded devices to create the operating system, which has many embedded devices, which requires CE operating system can be customized, so Microsoft Windows CE for the modular design of the operating system. That simple point, we can imagine Windows CE into a box of building blocks, you can use the modular structures any objects, but not necessarily to put all the building blocks are used

富士通单片机串口与CAN总线通信程序，单片机的类型为MB96F313，晶振选择类型需修改，嵌入式应用程序

PIC16F877_DS1302时钟程序，调试通过！-PIC16F877_DS1302 clock procedures, debugging through!

这是一个uC/OS-II For S3C44B0x的移植项目源代码．可以在uCOSV252.exe上运行，绝对可用-This is a uC/OS-II S3C44B0x For the migration project source code. UCOSV252.exe can run absolutely available

一个详细的计算器代码用minigui编的-A detailed calculator code series with minigui

verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline

由 Xilinx 提供的 IIC 接口，使用 AXI interface。 Features ‧ AXI interface is based on the AXI4-Lite interface ‧ Master or slave operation ‧ Multi-master operation ‧ Software selectable acknowledge bit ‧ Arbitration lost interrupt with automatic mode switching from master to slave ‧ Calling address identification interrupt with automatic mode switching from master to slave ‧ START and STOP signal generation and detection ‧ Repeated START signal generation ‧ Acknowledge bit generation and detection ‧ Bus busy detec ‧ Fast mode 400 KHz operation or standard mode 100 KHz ‧ 7-bit or 10-bit addressing ‧ General call enable or disable ‧ Transmit and receive FIFOs - 16 bytes deep ‧ Throttling ‧ General purpose output, 1 bit to 8 bits wide ‧ Dynamic Start and Stop generation ‧ Filtering on the SCL and SDA signals to eliminate spurious pulses

spi driver code one marve