用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0；...

DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

经过测试的 VHDL 代码为 18 x 18 位华莱士树乘法器

Programmable Logic Design Quick Start Guide from Xilin Co.

台湾产数字编码电位器EC11的使用测试程序(Taiwan-digital encoder potentiometer EC11 of testing procedures)

verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System

HARQ技术研究，以喷泉码为研究对象，结合LDPC纠错码而研究的。(HARQ technology research to fountain codes for the study, and research combined with LDPC error correction code.)

说明：  用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)

Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。(Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.)

this the for a equiripple filter-this is the for a equiripple filter