用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0；...

根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)-Electronic Design Competition works _ audio signal source analyzer FPGA (first prize)

用Verilog实现汉明码编码，经测试可正确使用，代码简洁(Verilog with Hamming code encoding, the test can be used correctly, the code is simple)

Hexadecimal to 7 segments

关于一款线阵CCD TCD1206UD 的驱动设计，波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)

本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation

并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers

altera的几种新型的FPGA的配置方法和使用心得-altera several new FPGA configuration methods and the use of experience

一个简单的23计数器，用VHDL实现，可供初学者学习。(A simple 23 counters, with the VHDL implementation, available for beginners.)

DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)