用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0；...

TFT 液晶屏显示，通过按键，显示不同的曲线(TFT LCD display)

source code for Ethernet logic

vhdl语言例程集锦.pdf，全部的例子，看你会不会偷了-VHDL language routines Collection. pdf, all the examples, you will not see stealing

altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera

ADS7870 Serial ADC Interface Using a CPLD, The system includes an XPLA3 CoolRunner CPLD, a Texas Instruments ADS7870 ADC, and a Toshiba SRAM, All related VHDL source code is provided

基于VHDL语言，实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)

VHDL上百实例 包括 ADDER LATCH FIPPER AND ETC..(VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..)

24位x24位的乘法器 十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)

说明：  本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)

设计一个具有同步置1，异步清零的D触发器。 设计一个类似74LS160的计数器(Design an D trigger with synchronous reset 1 and asynchronous reset. Design a counter like 74LS160.)