负数的三重移位

用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

本代码仿真了WCDMA小区搜索。cell_search_cpich scramble wcdmasource(This code emulation WCDMA cell search. cell_search_cpich scramble wcdmasource)

//顶层模块 //本次正弦波频率大约在750-800Hz，没有精确计算，和DA的加载时间有关 module DA_AD ( clk, rst_n, DAC_SCLK, DAC_DATA, DAC_LDAC, DAC_LOAD, ADC_SDO, ADC_SDI, ADC_SCLK, ADC_EOC, ADC_CS, ADC_FS, led1 ); input clk; input rst_n; output DAC_SCLK; output DAC_DATA; output DAC_LDAC; output DAC_LOAD; //AD相关 input ADC_SDO; //ADC转换完成输出的数据 input ADC_EOC; //ADC的转换完成输出信号 output ADC_SDI; //ADC的输入数据 output ADC_SCLK; //ADC时钟信号 output ADC_CS; //ADC片选,低有效 output ADC_FS; //DSP模式帧起始信号 output led1; wire DATA_EN; wire [7:0] Cordic2driver; wire start; TLC5620_driver ins_TLC5620_driver ( .clk(clk), .rst_n(rst_n), .DATA_IN(Cordic2driver), .DATA_EN(DATA_EN), .

基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)

生成bt656数据格式，针对视频adv7127芯片(Generate bt656 data format,)

DS18B20温度模块，LCD1602显示(DS18B20 Temperature Module, LCD1602 Display)

LTE is an abbreviation for Long Term Evolution.

ssb的调制与解调，包括信号的产生、乘法器、加噪、BPF、解调等部分。(ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section.)

Control Unit VHDL code. Xilinx Spartan 3E board