负数的三重移位

FPGA简单VGA彩条显示程序驱动程序640*480(FPGA simple VGA color display Driver 640* 480)

简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。(imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL. )

说明：  可调矩阵，最大32*32位浮点数乘法矩阵及仿真。(32*32 floating multiplication matrix)

decoder 2-4 digital core

OPSK调制解调。代码思路很清晰，也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)

xilinx verilog FPGA驱动AD9613 数据采集DEMO程序(Xilinx Verilog FPGA drives AD9613 data acquisition DEMO program.)

用三个按键控制pwm输出 key0控制是选着显示/改变频率或占空比 key1控制增加 key2控制减少 数码管显示频率或占空比 频率单位默认Hz（500-20KHz） 占空比范围（0.1-0.9）(Control PWM output with three keys Key0 controls display/change frequency or duty cycle optionally Key1 controls the increase Key2 controls are reduced Digital tube display frequency or duty ratio Frequency unit default Hz (500-20khz) Duty cycle range (0.1-0.9))

说明：  简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)

对delta sigma进行设计，实现delta sigma ADC的设计(this is use for delta sigma adc ,and design and achieve adc)

fpga 对sdram的读写 在quartus平台下可以仿真实现