三态总线 GPIO

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

这个是DE2上的SDRAM 四个端口的驱动代码，相当实用！(This is a four-port SDRAM on a DE2 driver code, very useful!)

原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)

GPS code nco（GPS接收机，基带处理模块中累加模块设计代码，用于码跟踪环。代码设计巧妙，避免了消耗FPGA中比较稀缺的硬件乘法器资源）

Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol

C源碼16C550 串口驅動，使用中斷收送RS232資料(16C550 UART Driver)

用FPGA实现dct变换。verilog语言实现，在quartus9.0中验证，含整个工程(dct transform verilog language in quartus9.0 verify, with the entire project)

RSA加密算法IP，用verilog实现，结构清晰，注释全面，其中包括verilog的源代码，testbench和日文的设计说明文档 ./RSA_tb.v ./RSA1024_RAM.v ./RSASpec2007Oct11.pdf

基于FPGA的视觉电生理图像刺激系统的设计(Based on the design of FPGA visual electrophysiology image stimulation system)

CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)