物理编码子层

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)

spartan 3E和verilog HDL的初学者极好的教材，本程序可直接下载到spartan实验板上运行。(Spartan 3E and Verilog HDL beginners excellent materials, the program can be downloaded directly to the spartan experimental board run.)

实现pwm波的输出，按键可调占空比的，可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes )

CRC24的verilog实现,LTE的3GPP 36.212里面对应的CRC添加(the implementation of CRC24 in verilog)

基于verilog语言的数据选择器，包括数据选择器的测试模块 (verilog language based on the data selector, including data selection for the test module)

it can add two numbers and shows the answer

使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)

说明：  8位RISC-CPU设计和测试文件，5位操作码支持32条指令，含堆栈实现子程序调用功能。(8-bit risc-cpu design and test file, 5-bit opcode supports 32 instructions, including stack to realize subroutine call function.)

实现fpga上交通灯的设计，可以在开发板上实现红绿灯(Design of traffic lights on FPGA)

Simulation and Synthesis Techniques for Asynchronous FIFO Design