使用 fifo 来交换不同的时钟

MCP4725实现的i2c驱动程序，通过DA转换实现函数发生器(MCP4725 come ture i2c drive program,Through da conversion function generator in English)

that file is different I2S example

- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)

说明：  802.16d 的卷积编码和解码的VHDL实现(802.16d cc encoding and decoding,writing in VHDL)

闹钟设计，VHDL，源代码。闹钟设计，VHDL，源代码。(Alarm clock design, VHDL, the source code.)

FPGA 的VGA显示应用。最大采样频率100M，共十个采样通道，存储深度为每通道1024位。带时间标线，显示区域可移动。最终将波形数据显示到VGA显示器上。用Quartus ii进行设计，仿真工作。最后可在开发板上进行硬件测试。

用VERILOG编写的VGA字符显示，可以在电脑屏幕上显示字符,已通过测试(Prepared with the VERILOG VGA character display, can display characters on a computer screen, has been tested)

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

基于DDS和SOPC的谐波信号发射器，拥有可调节的频率，阶段和谐波比例的谐波信号发射器由本文所设计。(Based on DDS and SOPC harmonic signal transmitter, with adjustable frequency, phase and harmonic proportion of harmonic signal transmitter designed by this article.)

a manual for design implementation of fpga and ASIC using verilog