ov7670数据读取

说明：  AXI verilog designs with testbench: AXI-lite, AXI, AXI-stream

32bit floating point addition

这个是 DDR3 SDRAM 控制器的 verilog 代码。欢迎下载和使用。谢谢您的支持！！！

双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT STATIC RAM)

说明：  EGO_1流水灯显示代码步骤过程全都有适合初学者练手(EGO_1 nxoiaocijpwjcpoewopvkpowevko)

vhdl数字电路设计经典教程，入门必备，非扫描版，非常清晰(vhdl digital circuit design classic handbook, entry-essential, non-scan version, very clear)

压缩包是ti xds100v3 Design kit的安装文件，安装后有原理图、PCB文件，与DSP接口采用FPGA，安装后有源码，是VHDL格式的，支持开源，降低开发成本(Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is VHDL formats, support for open source, reduce development costs)

说明：  lattice的官方8b10b代码, 1012年版本，diamond3.5编译。(lattice 8b10b encoder decoder code)

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)

用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！(Verilog FPGA internal 8051 core, super, super hard to find! Shared out!)