吠陀乘数使用拟议的 4 位加法器-(URDHVA TIRYAKBHYAM)

说明：  BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

这个项目是一个基于FPGA的alexnet第一卷积层实现。(This project is a FPGA based implementation of first Convolutional Layer of AlexNet.)

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)

说明：  串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)

fpga高手设计实战真经100则,最新的FPGA英文书籍，值得参考学习(100 Power Tips for FPGA Designers，The new FPGA English books, worth learning)

说明：  一个小寄存器堆，使用参数化编程，附有仿真代码，可直接在vivado（2018.2版本及以后）上运行(A small register heap, using parametric programming)

可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

关于SPWM调制设计VHDL代码 关于SPWM调制设计VHDL代码(SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM)