吠陀乘数使用拟议的 4 位加法器-(URDHVA TIRYAKBHYAM)

this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device

利用VHDL语言编写的4*4键盘扫描程序，经过测试，可以放心使用。(Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.)

nseval - Object evaluation, includes control method execution.

沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本(Walsh Function Generator)

FPGA verilog  的RS232代码， RS232是常用的PC与下位机通信的协议，而FPGA属于可编程器件，在目前的深度学习，机器视觉等领域应用前景十分良好， RS232对于新手FPGA有良好的借鉴作用

无需使用任何乘法器乘法运算。乘法是通过使用移位操作，并找出一些乘法创新的想法，无需使用乘数。

音频编码（ADPCM位） ；

ϵͳʱ

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.