2ASK调制解调的VERILOG程序代码

AMBA_APB verilog code

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。(I collected multiple VHDL language of sine wave generator SPWM program.)

xilinx zc706开发板Verilog流水灯源代码，适合刚开始接触FPGA的程序员，新接触xilinx ZYNQ-7000 zc706套件开发板的菜鸟，资源包含设计程序，仿真程序、综合程序，很简单的代码，适合初学者

ad9230的配置程序，差分输入输出，verilog(ad9230 configuration program, verilog)

FPGA通过AXI总线传输数据给ARM,ARM使用DMA方式接收数据！(FPGA to ARM Bridge design example)

讲述软解调很不错的一片文档，主要阐述的是8PSK的软解调FPGA实现，但对8PSK的软解调原理阐述很清楚，没有多余的东西，但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)

还好用，大家一起来看下，不错的图书管理软件啊 ，呵呵(Fortunately with, everyone look, the good library management software, ah, huh, huh)