FPGA实现UART接收和发送

很有用的ＳＤＲＡＭ读写代码，上板验证有效

BCD to 7 segments display decoder

The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).

16点FFT，简单易理解，适合初学者了解(16 point FFT, simple and easy to understand, suitable for beginners to understand)

xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)

vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

计算三平动并联机构工作空间，自己编的，测试可以用(Calculation of three translation parallel mechanism)

资源描述基于FPGA v5的ram制作以及测试啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊。。。

配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)