DE2_115_TV开发板例程，含SDRAM及异步FIFO应用

这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。 (This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)

RTL8369开发资料，包括手册，图纸，Layout说明等等(RTL8369 development information, including manuals, drawings, Layout Guide.)

本代码是cache代码，采用最近最少使用算法。代码量大约1000-2000行，程序包括cache替换算法的实现。映像规则的选择，以及全部的仿真程序。

64-point FFT/IFFT processor architecture : Rrdix-SDF

vhdl编写的4X4键盘扫描程序，可以有效的消除抖动，并且提供蜂鸣器输出。(VHDL prepared 4X4 keyboard scanner, you can effectively eliminate jitter and provide buzzer output.)

FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页(MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247)

本程序用以驱动安捷伦频谱仪和脉冲信号发生器，以产生格雷码波形。(It is aim to driver the PSG and ESA to generate Golay.)

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)

FPGA的测频程序，用了D触发器，能测1hz到几百hz(FPGA frequency measurement procedures, using a D flip-flop, can be measured to a few hundred hz 1hz)

说明：  MATLAB to HDL Code conversion