洗衣机verilog编程

xilinx V5板子，用来驱动DVI显示的Verilog代码。 可正常显示所需要显示的正常颜色和图案。 将CH7301芯片接到到的视频数据信号，直接显示到DVI显示屏上。

LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)

以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)

用Verilog实现汉明码编码，经测试可正确使用，代码简洁(Verilog with Hamming code encoding, the test can be used correctly, the code is simple)

基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)

max plus的入门与应用，适合初学者对max plus ii有一个感性的认识(max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of)

通过verilog语言实现各种基本信号的调制解调过程，包括2psk,qpsk,ppm(Realize the modulation and demodulation process of various basic signals through verilog language, including 2psk, qpsk, ppm)

多周期CPU源代码 verilog 自己写的 有仿真 实现了22条指令 比较完善 计算机组成课上的作业 没有根据实验书写，是自己实现的，代码稍微繁杂

在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)

FAST HADAMARD TRANSFORM VERILOG FOR IMAGE PROCESSING