数字钟，带调时加闪烁

说明：  一种用verilog语言实现的霍夫曼压缩编码算法(Huffman compression implemented by Verilog)

说明：  DFT FPGA实现,simulink到vivado(DFT FPAG implement base on simulink and HLS)

BUS documentation and map reffereces

提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)

连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)

It is vhdl code for defining a finite state machine

用Quartus II开发的一个十进制计数器，包括仿真波形，下载文件，是完整工程。(With the Quartus II development of a decimal counter, including the simulation waveform, download files, is the complete project.)

fpga的RS485代码,非常容易，适合学习(the code of rs485 in fpga, very easy,suitable for learning)

这是一个计算器的Verilog代码，可实现加减乘除等基础功能(calcultor for you to do some reserches.)

AD8176的控制verilog编写，可实现RGB的自由切换，16通道进，9通道输出。