verilog program for real time clock.. select the .v file to view the code.

FPGA入门点亮一个LED灯，作为FPGA入门级程序(FPGA is)

4、各个功能的主要源程序 1、移相模块： = 1 * GB2 * MERGEFORMAT ⑴、相位累加器： architecture one of add32 is begin   s

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)

我们使用此代码开发 plc 在 fpga 硬件计数器的程序

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

source vhdl code of D flipflop logic

基于FPGA的RS编码器设计，verilog hdl语言。(RS encoder FPGA-based design, verilog hdl language.)

基于Max+Plus II和VHDL的电子密码锁设计(Based on Max+ Plus II electronic lock and VHDL design)

dds 频率可控，32位 输出为12位 已含有.hex文件，直接装载致ROM即可~(dds frequency-controlled, 32-bit output is 12 already contains. hex file can be loaded directly caused ROM ~)