LDPC编译码

说明：  xilinx fpga各版本mmcm/pll动态配置RTL代码，包括testbench(xilinx fpga mmcm/pll drp RTL code, including testbench)

数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)

基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)

说明：  通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。 (As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)

stepper motor vhdl pin assignments and code

12232型号LCD液晶屏显示程序，简单易懂(12232 Model LCD screen display program, easy to understand)

CFI控制器顶层模块，32位wishbone总线经典接口，用于简化对CFI flash(如块)的访问解锁、删除和编程。(Top level of CFI controller with 32-bit Wishbone classic interface)

PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)