mips 程序

基于FPGA的视觉电生理图像刺激系统的设计(Based on the design of FPGA visual electrophysiology image stimulation system)

ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

ATM的功能工作.atmatmamtmtmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt

电路在语言中建模与入席，保存和显示数据与一个重置按钮 7 分割。

说明：  4位加法器，4位数字相加及进位功能的实现，主要利用Verilog语言实现，简单轻松，且代码量少(a adder which can realize 4 bit numbers adding)

说明：  此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)

FPGA很有价值的27实例.rar 包括 LED控制VHDL程序与仿真 2004.8修改.doc； LED控制VHDL程序与仿真； LCD控制VHDL程序与仿真 2004.8修改； LCD控制VHDL程序与仿真； ADC0809 VHDL控制程序； TLC5510 VHDL控制程序； DAC0832 接口电路程序； TLC7524接口电路程序； URAT VHDL程序与仿真； ASK调制与解调VHDL程序及仿真； FSK调制与解调VHDL程序及仿真； PSK调制与解调VHDL程序及仿真； MASK调制VHDL程序及仿真； MFSK调制VHDL程序及仿真； MPSK调制与解调VHDL程序与仿真； 基带码发生器程序设计与仿真； 频率计程序设计与仿真； 采用等精度测频原理的频率计程序与仿真； 电子琴程序设计与仿真 2004.8修改； 电子琴程序设计与仿真； 电梯控制器程序设计与仿真； 电子时钟VHDL程序与仿真； 自动售货机VHDL程序与仿真； 出租车计价器VHDL程序与仿真 2004.8修改； 出租车计价器VHDL程序与仿真； 波形发生程序； 步进电机定位控制系统VHDL程序与仿(FPGA value of the 27 examples. Rar including LED control procedures and VHDL simulation 200 4.8 amendments. doc; LED control procedures and VHDL simulation; LCD control procedures and VHDL simulation 2004.8 modified; LCD control procedures and VHDL simulation; Connection between ADC 0809 VHDL control procedures; TLC5510 VHDL control procedures; DAC0832 interface circuits; TLC7524 interface circuits; URAT procedures and VHDL simulation; ASK modulation and demodulation process and VHDL simulation; FSK modulation and demodulation process and VHDL simulation; PSK modulation and demodulation process and VHDL simulation; MASK modulation procedures and VHDL simulation; MFSK modulation procedures and VHDL simulation; MPSK modulation and demodulation process and VHDL simulation; Base-band code gene)

资源描述 说明： 结绳模块(Pluse2Toggle): 负责延长待采样信号 同步模块(Synchronization)：负责双触发器锁存 解绳模块(Toggle2Pluse)： 负责将长信号转换成脉冲信号 支持信号从快时钟域到慢时钟域，也支持信号从满时钟域到快时钟域，

无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)

Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )