CODE_VHDL_COUNTING 电路时钟运动显示期间 LED 7 （MẠCH ĐẾM ĐỒNG HỒ THỂ 邵族 HIỂN THỊ 领导 7 ĐOẠN）

VHDL语言实现的16位快速乘法器-VHDL of 16 rapid Multiplier

用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。(the source code for driving VGA and displaying the images,the testbench was offered.)

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

ldpc码的FPGA编译与仿真实现，欢迎分享，分享快乐。(LDPC code compilation and simulation。)

彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

FPGA资料与所用元器件的数据参考手册与应用指南(ds312_Spartan-3E FPGA Family )

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)