CODE_VHDL_COUNTING 电路时钟运动显示期间 LED 7 （MẠCH ĐẾM ĐỒNG HỒ THỂ 邵族 HIỂN THỊ 领导 7 ĐOẠN）

wishbone接口的设计，在交换机和MAC之间建立wishbone接口(the wishbone interface design, wishbone interface between the switch and MAC)

This file contains async fifo design

用可编程逻辑器件实现PWM波形即PWM波形发生器-Using programmable logic devices that realize PWM waveform PWM Waveform Generator

FPGA设计的四种常用思想与技巧分享:串并转换设计技巧、流水线设计思想……(FPGA design of four common ideas and techniques)

片上网络NOC基于fpga实现的，routing模块。(NOC-chip networks realized fpga-based, routing module.)

IIC总线协议，VHDL语言编写，可以直接使用-IIC bus protocol, VHDL language can be used directly

FPGA神经网络设计（影印本），全英文，很有用(FPGA neural network design (photocopies), all in English, very useful)

基于vhdl编写的贪吃蛇游戏，课程设计必备(Based on the VHDL language of the snake game, curriculum design essential)

说明：  fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

sub opercore USB CRC5 and CRC16 Modules //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/(sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/)