uart-gen.rar

说明：  BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

说明：  422发送源码，目前使用的是20m时钟计算出来的波特率，后期可以根据自己的需要进行修改波特率时期匹配各种情况(422 sends the source code. At present, the baud rate calculated by 20m clock is used. Later, you can modify the baud rate according to your own needs to match various situations)

本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)

vmm primer的使用使用文档，和之前vmm primer源代码配套使用！(vmm the primer use of the use of the document, and before supporting vmm the primer the source code to use!)

基于PCI总线和LPC接口的POST主板诊断卡代码，已经通过fpga测试可以使用，性能非常稳定。(Based on the PCI bus and LPC POST motherboard diagnostic card code to interface fpga has passed the test can be used, the performance is very stable.)

用fpga实现的连连看游戏，功能还不完善，不过可以借鉴。(Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.)

Matlab agc ʵ

verilog alu 8bit for engineers

使用Verilog编写的ad9826的控制模块(the module of ad9826 with verilog)

说明：  用uvm验证方法学验证异步fifo，文件包括异步FIFOrtl代码和uvm组件(Verification of asynchronous FIFO with UVM)