数字频率合成原理

PCI slave IP core, in VHDL language ,has been verified,it is very easy to use. it is an ideal IP to study PCI,design PCI Bridge

基于FPGA的1602时钟显示,驱动1602显示时钟,矩阵键盘调时(1602 FPGA-based clock display, clock display driver 1602, when the transfer matrix keyboard)

In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.)

can总线通信参考资料，实现can总线通信传输

一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)

vhdl code for carry lookahead addder

Verilog 实验代码。。。经典的，里面都是完整的项目文件。 ISE环境。(Verilog test code. . . Classic, which is a complete project file. ISE environment.)

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )

采用uvm-1.1d system verilog lib uvm可用于大规模仿真验证测试 配套example code提供了从入门级到深入学习的code，在modelsim 10.2c版本上运行成功了

使用两个8点FFT完成64-point FFT(64-point FFT)