FPGA驱动VGA显示彩条

this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

说明：  30 bus for atp design

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 (I am learning more systematic series of practical VHDL source Giant)

PCIE仿真设计教程1-6，我帮大家收集到一起了(PCIE simulation design tutorial 1-6, I help you gather together.)

说明：  基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

SDRAM驱动器，自己项目利用的，已经经过实际验证(sdram controller)

基于Verilog的串口通信源码 ，实现串口通信功能(Verilog source code based on serial communication)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

运用quartus 软件模拟的电子琴，实现按键出现不同音调的音乐。(Quartus software simulation using keyboard, keys appear to achieve different tones of music.)