四位十进制频率计的源代码,详细,清楚地写出了设计语句

ldd2的e文原版，找得辛苦，比中文版（错误不少）好-e ldd2 the original text, hard to find than English (many errors) good

windows ce 设备驱动程序开发指南-windows ce device driver development guide

thinking in java中文版，很经典得一本java书籍-thinking in java the Chinese version was a classic java books

java book with an example

研华函数参考手册，为研华板卡的编程提供方便，希望对大家有用-Advantech function reference manual for the Advantech board to facilitate programming, in the hope that useful to everybody

modern control systems, 11th edition, dorf-modern control systems design, application & simulation

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

C++primer4中文版，chm格式，很清晰-C++ Primer4 Chinese version, chm format, it is clear

学习j2ee设计模式的好书-learning design patterns creates books

包含各类数据结构问题的常用算法，非常有用，但用一些问题-Types of data structure that contains the common algorithm, is very useful, but with some problems