基于LMS 算法的多麦克风降噪
武汉理工大学 信息处理课设 基于LMS 算法的多麦克风降噪 给定主麦克风录制的受噪声污染的语音信号和参考麦克风录制的噪声，实现语音增强的目标，得到清晰的语音信号。2007控制科学与工程全国博士生学术论坛2007年8月其中日为语音信号与麦克风阵列所在平面的夹角,d为麦克风间距,c为声音传播速度,f为信号采样率。固定波束形成器通过延时求和单元产生参考语音信号y(n),y(n)与y(m)分别代表期望语音信号与噪声信号。y,(n)4x(m)=y(m)+y/(m(3)信号通过阻塞矩阵产生噪声参考信号用来估计波束形成输出信号中的噪声成分。选取B使其中任意行向量之和为零,即任意行向量线性无关。为了进一步降低噪声参考信号中的语音泄漏,参考文献“提出了用自适应阻塞矩阵替代固定阻塞矩阵的方法。ynly2nMM-[nJ]=BLun], u2n],umn自适应噪声抵消器ANC通过对输入噪声参考信号进行自适应滤波处理抵消了参考信号y,(m)中的噪声成分,得到增强的语音信号。em]=y[m-∑nnl3LMS自适应算法及改进31LMS自适应算法GSC架构中的自适应噪声抵消器ANC需要用增强的语音信号作为反馈对滤波器权值进行自适应更新。很多自适应算法基于LMS及其改进形式, Clark提出的块LMS算法使得滤波器的自适应逐块更新而非传统LMS滤波器逐点更新4, HOSHUYAMA、 Kellermann分别提出的基于范数约束自适应算法的权值更新,以及频域无约束实现。这些算法基本结构如图2所示y(n-1)(n-L+1)wo(ne(ny/(n)图2自适应横向滤波器结构图图2为图1中的M-1路L阶多通道自适应噪声对消器中某一路的展开形式,其抽头输入向量为[ym]yn-]yn-L+1],对应的抽头权向量为wmwn]w-]。LMS算法的梯度向量通过G2007控制科学与工程全国博士生学术论坛2007年8月计算抽头输入相关矩阵R和抽头输入与期望响应间互相关向量p得到VJ(n)=-2p+2Rv(m),将R和p的瞬态估计R(n)=y(m)y"(n),p(n)=y(n)y/(m)代入,得出梯度向量的瞬态估计:VJ(n)=-2y(n)y, (n+2y(n)y"(n)w(n)进而推出LMS算法权值更新公式为w(n+1)=w(n)+uy(n)Ly(n)-y"(n)w(n)32基于稳态噪声的自适应算法改进考查图2中具有L个抽头权值的LMS算法,抽头权值与抽头输入一一对应。在传统的逐点更新LMS算法中,每计算一个输出需要L次乘法,而更新一次抽头权值也需要L次乘法,故每次迭代需要2L次乘法。对于L个输出样值,所需要的乘法次数为2次。针对传统LMS算法复杂度高的缺点,Ca利用离散傅立叶变换在频域完成滤波器系数的自适应提出了快速块LMS箅法, Ann Spriet在此基础上通过改进LMS算法中的步长矩阵进一步降低了算法复杂度以上LMS算法改进均在图2的横向滤波器架构下进行,即抽头权值与抽头输入一一对应。考虑到稳态噪声的特点,本文提出了“一对多”的滤波器抽头权值更新算法,即L个输入样值共享一个滤波器权值。如此M路多麦克风语音增强系统中的ANC滤波器权值便由(M-1)×L维矩阵W[n=[w[η],n2[rl…wM-[r],其中H[n]=[won],w1[nw-r]退化为(M-1)×1维向量n]=[wryw2n],M-m]j。改进算法权值更新公式为w(n+D)=w(n)+uBu(nu"(n)[A-Bw(n)其中B为阻塞矩阵,A为固定波束形成器,为步长,U(n)为LxM维输入信号。与传统的“一对一”LMS滤波器相比,“一对多”结构在降低算法复杂度的同时,牺牲了前者具有的时间域严格对齐的特性。为降低这一缺点对系统降噪性能的影响,应在频域进行噪声对消,改进算法的多麦克风语音增强系统结构如图3所示。e(n)(n)B Yn图3改进的噪声消除算法结构图3中用虚线框表示可选滤波器权值w。由于实际应用中语音泄漏的存在,在参考语音信号中加入v能有效补偿由语音泄漏引起的语音崎变⑩。实际应用中由于阻塞矩阵输出不可避免的存在语音泄4642007控制科学与工程全国博士生学术论坛2007年8月漏,为了避免期望信号的消除,箅法中加入语音活动检测单元89,当前帧为噪声时更新滤波器系数,当前帧为语音信号时,滤波器系数不变33算法复杂度比较表1列出了本文算法与其他几种噪声消除算法之间算法复杂度的比较。我们采用实数乘法运算次数作为衡量算法复杂度的标准,每个N点傅立叶变换或其反变换需要Mlog2N次实数乘法运算。传统逐点LMS算法在时间域逐点更新滤波器权值。快速块LMS算法与多通道 Wiener算法通过FFT快速循环卷积特性实现LMS中的线性卷积运算,从而降低算法复杂度。本文算法在此基础上通过改进滤波器抽头权值更新算法进一步降低运算复杂度。由表1可见,当麦克风数目M4,L=32时,本文算法与多通道 Wiener滤波算法相比,R(3M+2)FT+8ML+2M63M+2)+4M2+6M_172(M+2)FFT+2ML6(M+2)+M40°文算法运算量降低了4倍左右。表1算法复杂度比较算法名称算法复杂度传统逐点LMS算法2ML快速块LMS算法(41(3M+2)FFT+16ML多通道 Wiener滤波算法53M+2)FFT+8M2+12M本文提出的算法(M+2)FF+2M…图4a)麦克风采集到的原始信号b)采用快速块LMS算法处理后的信号[4]c)采用多通道 Wiener滤波算法[10处理后的信号d采用本文算法处理后的信号4实验结果与分析实验采用线性排列的4个间距为4厘米的麦克风组成的语音采集系统,采样率为44KHZ,说话人位于阵列的正前方,噪声为稳态噪声,其与麦克风阵列法线所夹角度为50度。图4比较了麦克风采集到的信号、采用本文算法处理后的语音信号以及采用其他主流语音增强算法处理后的语音信号的时域波形。由4652007控制科学与工程全国博士生学术论坛2007年8月图4可见采用本文算法处理的语音信号背景噪声有明显降低。为进一步分析各种语音增强算法消噪能力,分别按照公式9计算各算法输出信号的信噪比,其中k代表帧序列号,N代表噪声,Y代表输出语音信号,L为帧长。∑(Y(k,2)2-|N(k,)SNRou(E)=10 log,o∑1MV6)图5釆用各箅法输出信号信噪比与输入信号信噪比之差来衡量噪声降低程度。由图5看出,在本文算法基础上在参考通道中加入可选滤波器权值能够进一步消除背景噪声,提高输出信噪比。苯文鲜法(使用权值w)木文好法未使用权值y块LMS算法Frame Number图5信噪比增强对比5结论本文在稳态噪声的前提下,提出了一种基于广义旁瓣消除器架构具有低算法复杂度的噪声消除算法,该算法通过改进LMS滤波器权值更新算法来达到降低算法复杂度的目的。实验结果证明,在稳态噪声环境下,该方法降噪性能优于传统LMS算法,同时有效降低了传统算法的算法复杂度。在现实生活中一些存在稳态噪声的场合,如发动机舱、厂房等该算法具有很强的实用价值。参考文献[U]LJ. Griffiths and C. W. Jim []. "An altemative approach to linearly constrained adaptive beamforming, IEEE Trans. AntennasProcess., voL. AP-30, no. I, pp 27-34, Jan. 1982.[2]0. Hoshuyama, A Sugiyama, and A Hirano [J]. "A robust adaptive beamformer for microphone arrays with a blocking matrixusing constrained adaptive filters, "IEEE Trans. Signal Process. vol 47, pp. 2677-2683, Oct. 1999[3]W. Herbordt and W Kellermann [J]. " Frequency-domain integration of acoustic echo cancellation and a generalized sidelobecanceller with improved robustness, "Eur. Trans. Telecommun., voL. 13, no 2, pp 123-132, Mar. -Apr. 2002.[4]Clark. G.A., S K Mitra, and S.R. Parker [J]. Block implementation of adaptive digital filters, "IEEE Trans. Circuits Syst,voL. CAS-28,PP584-592.1981.[5]Ann Spriet, Jan Wouters, Simon Doclo, Marc Moonen, "Frequency-Domain Criterion for the Speech Distortion WeightedMultichannel Wiener Filter for Robust Noise Reduction", Ap: //ftp. esat kuleuven. ac, be/pub/SISTA/doclo/reports/04-240 pdf[6JH. Buchner, J. Benesty, W. Kellermann J]. Generalized multichannel frequencydomain adaptive filtering: efficient realizationand application to hands free speech communication", Signal Processing 85(3), PP 549-570. 2005[7]W.Herbordt and W. Kellermann [A]. " Efficient Frequency-domain realization of robust generalized sidelobe cancellers", IEEE4662007控制科学与工程全国博士生学术论坛2007年8月Fourth workshop, multimedia signal Processing, PP. 377-382 2001[8]S. Van Gerven, F. Xie [J. "A Comparative Study of Speech Detection Methods", Proc. EUROSPEECH, VoL 3, Rhodos, Greecepp.1095-1098.1997[9]J Sohn, N.S.Kim, W Sung [] A Statistical Model-Based Voice Activity Detection", IEEE Signal Processing Lett. 6(1)1-31999[10]A Spriet, M. Moonen, J Wouters[]. Robustness Analysis of Multi-channel wiener Filtering and generalized sidelobeCancellation for Multi-microphone Noise Reduction in Hearing Aid Applications", IEEE Trans. Speech and Audio Processing, 13(4)PP.487-503.2005[IlJFerrara, E R r [] Fast implementation of LMS adaptive filters", IEEE Trans. Acoust. Speech Signal Process,voL.ASSP-28pp474-475.1980[12]S. Doclo and M. Moonen[J]. " Multi-microphone noise reduction using recursive GSVD-based optimal filtering with ANCpostprocessing stage, "IEEE Trans. Speech Audio Process., vol. 13, no. 1,Pp 53-69, Jan. 2005[13]Philipos C Loizou [J]. "Speech Enhancement Based on Perceptually Motivated Bayesian Estimators of the MagnitudeSpectrum" IEEE TRANSACTIONS ON SPEECH AND AUDIO PROCESSING, VOL 13, NO 5, Pp.857-869, 2005种新的基于稳态噪声的噪声消除算法旧WANFANG DATA文献链接作者:董鹏宇,朱子元,林涛作者单位:同济大学超大规模集成电路研究所,上海20009本文链接http://d.g.wanfangdata.comcn/confereNce6584700.aspx
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全志 F1C600完整手册
The F1C600 processor represents Allwinner’s latest achievement in mobile applications processors. The processor targets the needs of boombox markets. F1C600 processor is based on the ARM9 CPU architecture with a high degree of functional integration. F1C600 supports Full HD video playback, iAllwinnerTechnologyRevision HistoryRevision historyVersionateDescriptionV1.0NoV10,2015nitia|Re|ease∨ersⅰonF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 3AllwinnerTechnologyRevision HistoryTable of contentsDeclaration2Revision histeD。着,着垂Table of contents.:::::.:::::1:4Chapter 1.About This Documentation361.1 Documentation overview36Chapter 2 Overview....372.1 Processor features2.1.1, CPU Architecture2.2. Memory Subsystem....................382.2.1. Boot rom382.2.2 SDRAM382.2.3. SD/MMC Interface..:::··:·.:::::..:·.:::::::::::··:382.3. System Peripheral.382.3.1. Timer.382.3.2.|NT392.3.3.CCU392.3.4.DMA,392.3.5.PWM,392.4. Display subsystem39241. Display engine…,,…...:::::392.4.2. Display output.....39F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 4AllwinnerTechnologyRevision History2.5. Video Engine26.| mage Subsystem…D看看1,翻看、·着国,着,,,面面,2.6.1.CS|4看402.6. 2 CVBS Input402. 7. Audio Subsystem2.7.1, Audio codec2.8. System Peripherals2.8.1.USB2.00TG412.8.2. KEYADC412.8.3.Tl:::::412.8.4. Digital Audio Interface.....................2.8.5.UART412.8.6.SP412.8.7.TW|422.8.8.CIR422.8.9,RSB422.8.10.OWA.422.9 Package422.10. System block Diagram43Chapter3. System..........................,443.1. Memory Mapping….453.2. CCU2463.21 Overy3.2.2, FeatureF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 5AllwinnerTechnologyRevision History3.2.3. Functionalities Description3.23.1. System bus….:.:::..a...:::::::非3.23.2 Bus clock tree473.2.4. CCU Register List…….473.2.5. CCU Register Description483.2.5. 1 PLL CPU Control Register3.2.5.2. PLL AUDIO Control register......................493.2.5.3. PLL VIDEO Control Register503.2.5.4. PLL VE Control Register513.2.5.5. PLL DDR Control Register3.2.5.6. PLL PERIPH Control Register...............523.2.5.7. CPU Clock Source register533.2.5.8. AHB/APB/HCLKC Configuration Register543.2.5.9. Bus Clock Gating Register O.......553.2.5. 10. Bus Clock Gating Register 1................553. 2.5.11. Bus Clock Gating Register 2563.2.5.12. SDMMCO Clock Register583.2.5.13. SDMMCl Clock Register.58325.14. DAUDIO Clock Register……593.2.5.15. OWA Clock Register.........................593.2.5.16. CIR Clock Register.603.2.5.17. USBPHY Clock Register603.2.5. 18 DRAM Gating register.603.2.5. 19 BE Clock Register61F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 6AllwinnerTechnologyRevision History3.2.5.20. FE Clock Register623. 2.5.21. TCON Clock Register623.2.5.22. De-interlacer Clock Register623.2.5.23. TVE Clock Register∴633.25.24. TVD Clock Register……643.2.5.25. CSI Clock Register643.2.5.26. VE Clock Register.......653.2.5.27. AUDIO CODEC Clock Register653.2.5.28. AVS Clock Register.653.2.5.29. PLL Stable Time register 0653.2.5.30. PLL Stable Time Register 1...............................................................653.2.5.31. PLL CPU Bias register663.2.5.32. PLL AUDIO Bias Register663.2.5.33. PLL VIDEO Bias Register663.2.5. 34 PLL VE Bias Register673.2.5.35.PLL_ DDR Bias Register…..,…,…,…673.2.5.36.PLL_PER| PH Bias Register……673.2.537.PLL_ CPU Tuning Register.……683.2.5.38. PLL DDR Tuning Register683.2.5.39. PLL AUDIO Pattern Control register........................693.2.5.40. PLL VIDEO Pattern Control Register.693.2.5. 41. PLL DDR Pattern Control Register3.2.5.42. Bus Software Reset Register O..3.2.5.43. Bus Software Reset register 1F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 7AllwinnerTechnologyRevision History3.2.5.44. Bus Software Reset Register 23.2.6. Programming guidelines3.2.6.1.PLL4看3.2.6.2.BUS3.3. Timer743.3 1. Overvi翻着看743.3.2, Feature…743.3.3. Functionalities Description..743.3.3.1. Typical Applications743.3.3.2. Functional block Diagram753.3.4.Timer Register List.......................753.3.5. Timer Register Description3.3.5.1. Timer IRQ Enable Register...763.3.5.2. Timer iRQ Status Register3.3.5.3. Timer 0 Control Register3.3.5.4. Timer o Interval value register .................................3.3.5.5. Timer 0 Current Value Register3.3.5.6. Timer 1 Control Register....3.3.5.7. Timer 1 Interval value register,7933.58. Timer1 Current Value Register…....…793.3.5.9. T imer 2 Control register3.3.5.10. Timer 2 Interval value Register803.3.5. 11 Timer 2 Current Value register3.3.5. 12 AVS Counter Control Register81F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 8AllwinnerTechnologyRevision History3.3.5.13. AVS Counter O Register.81335.14. AyS Counter1 Register.,,…,;…,…,…,…813.3.5.15. AVS Counter Divisor Register….,.,,,,…,,…3.3.5.16. Watchdog irQ Enable Register.………823.3.5.17. Watchdog statusster823.3.5.18. Watchdog Control Register83335.19. Watchdog Configuration Register……,,,…833.3.5.20. Watchdog Mode register....833.3.6. Programming Guidelines843.3.6.1. Timer,,84336.2. Watchdog….…843. 4, PWM853.4.1. Overview853.4.2 Feature853.4.3. Functionalities Description853. 1. Functional Block Diagram......着,着面853.4.4. Operation Principle863. 4.4.1. PWM output pins863.4.5. PWM Register List……3.4.6. PWM Register Description.....................3.4.6.1. PWM Control Register.3.4.6.2. PWM Channel 0 Period Register883.4.6.3. PWM Channel 1 Period register893.5.NTC.90F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 9AllwinnerTechnologyRevision History3.5.1. Overview903.5.2, Feature.:..:.:::::a:::.:::.:.a..:::::.:::::903.5.3. Functionalities Description903.5.3.1. Functional Block Diagram903.5.4.Interrupt source913.5.5. INTC Register List.....................................3.5.6. INTC Register Description…923.5.6.1. Interrupt Vector Register.……923.5.6.2. Interrupt base Address register933.5.6.3. NMI Interrupt Control Register933.5.6.4. Interrupt irQ Pending register o933.5.6.5. Interrupt iRQ Pending register 1...............933.5.6.6. Interrupt Enable register o933.5.6.7. Interrupt Enable Register 1.............933.5.6.8. Interrupt Mask register 0943.5.6.9. Interrupt Mask Register 1.::::943.5.6.10. Interrupt Response Register O.......943.5.6.11. Interrupt Response Register 1943.5.6.12. Interrupt Fast Forcing register 0943.5.6.13. Interrupt Fast Forcing Register 1....................................................................953.5.6. 14 Interrupt Source Priority Register O953.5.6.15. Interrupt Source Priority Register 1...973.5.6.16. Interrupt Source priority register 21003.5.6. 17 Interrupt source priority register 3102F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 10
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