STM32移植到GD32的注意事项
GD32的性价比和稳定性都很高。我更喜欢用GD32.。但不是100%兼容的。需要注意一些细节。2.内部 Flash1)芯片设置读保护用法描述由于GD的Fash是自己的专利技术,STM的Fash是第三方提供的,所以GD的 Flash和STM的Fash有些许差异。GD的擦除时间会长一点解决方法在写完KEY序列以后,需要读该位,确认key已生效。所以,这里应该插入While(! (FLASH->CR &0x200);//Wait OPTWRE或可简单插入两个NOPNOPONOPO在ST库中,只有FLASH Status FLaSH Erase Option Bytes(void)FLaSH Status FlaSH ProgramOption Byte Data(uint32 t Address, uint8 t DataFLASH Status FLASH_ Enable WriteProtectionuint32 t FLASH PagesFLASH Status FLASH ReadOutProtection (Functional State New State)四个函数需要修改。2)IAP在应用中编程描述GD32由于有fash的0访问时序,同SM32在Fash的Ease和 Program上存在差别,GD32的 Erase和 Program时间比STM32的稍微长些建议对 Erase和 Progran时间进行修改解决方法将宏定义井 define erase timeout(luint32 t)OX000B000O)#define ProgramTimeout(uint32_t)ox00002000修改为:#define erasetimeout((uint32_t)OX00OFFFFF#define ProgramTimeout(uint32 t)OxOOOOFFFF备注: Erase和 Program时间宏定义在stm3210 x flash. c源文件中路径: braiesSTM32F10 x Std Periph Driversr)3)用IAR下载配置解决方法在批量牛产的时候首先会烧写一个USB的boot,这个boot自动运行后在由上位机软件进行烧写应用程序。如果boot程序不能自动运行则需要重新插拔次电源。给生产造成一些麻烦。产生不能自动运行程序的原因是如果程序设置读保护的话需要等待 FLASH CR的第9[ OPTWRE]位为1.如果没有置位的话继续执行就会出错。由」ST的执行速度慢,程序执行到读 FLASH CR寄存器的时候该位已经置1,GD的执行速度比较快,程序运行到这的时候该位还没置1,因此需要在 FLASH ReadOut Protection函数里面添加一些轮询该位为1或者加延时3.ISP烧写软件1)ISP烧写,建议使用官方烧写软件性述芯片内部同有区别解决方法建以到下载最新版本的另外也有专门的烧写软件(可以到论坛下毂如果使用自制的软件或脱机编程器,实现和完全兼容,建议修改以下参数。页擦除等待超时时间增加至整片擦除等待超时时间增加至左右字编程等待超时时间增加至,臾编程等笭超时时间增加至I/0日1)I0口外部中断使用方法措述在关闭期间,如果外部引脚有电平的变化,在使用MR打开中断后会马上进入中断服务程序。理论是打开中断前,不管管脚是否有电平的变化,都不会影响到打开后的中断响应。解决方法所以解决方法就是通过禁用上升沿或者下降沿检测寄存器来开关中断,不能使用IMR屏蔽奇存器。程序如下关闭沿检测,以达到关闭中断的目的,下降沿使用寄存器,上升沿使用寄存器2)在待机模式,PA8引脚特殊设置描述在使用低功耗的情况下,PA8会被MCU在内部被设置为地PA8复用为MU内部频率输出,超低功耗设时需要悬空解决方法在待机模式,PA8悬空不用3)低功耗下必须注意描述在使用低功耗情况下,把软件全部端口(AF)时钟关掉,无论是否有该端凵。4)当有脉冲群冲击管脚摧述需要在在进入中断后关闭中断4.定时器1)定时器输入捕获模式需要软件清中断描述sTM定吋时器输入捕获模式默认能硬件清中断,GD为了更加严格要求配置,需要做软件清中断解决方法软件清除标志位2)定时器向上脉冲计数模式设置述定时器的用法差异解决方法脉冲计数模式下,装载值必须设置为比预期值大,否则不计数在ST上如果重载值不设置(初始为0)的时候,CNT可以正常计数。在GD上如果重载值不设置保持初始为0的时候,会因为重载值为零,即便是来一个脉冲也会导致所有的寄存器复位从而不能正常计数。型号GD32F1系列MCUF|ah256B8及以上的型号)3)TIM、ADC模块描述Tmer、ADC模块的触发信号宽度要求解决方法|由于内部有高速和低速两条外围总线,Tmer、ADC模块和其他外设共同使用这两个总线。GD32F103/101系列Fash128KB及以下的型号, Timer、ADC等模块识別触发信号的条件是触发信号宽度大于模块所在总线的时钟宽度5.串口 USART1) USART连续发送数据字节有空闲位带述字节间有空闲位解决方法|对于一般的通讯米说,不会有影响,只对于一般在通讯上有特殊协议的,才会产生数据不准确的情况所以,特定情况,修改程序6.I2C总线1)硬件L2C特殊配置述GD的C相对STM的来说要少一个标志位解决、宏地址定义改交方法2、硬件I2C在会在向从机发送7bits地址完成后,从札还没来得及识别。(看客户应用)我们可以在发送完7bits后加个延时,让从机完全识别I2C Send7bitAddress(I2C1, EEPROM ADDRESS, I2C Direction TransmitterintOfffhile(i --3、检测ADDR不能使用I2 C Checkevent函数,因为他会清除ADR,可以使用I2 C Get FlagStatus函数就是把while(! I2C CheckEvent(I2C1I2C EVENT MASTER TRANSMITTER MODE SELECTED))Ey while(! I2C GetFlagStatus(I2C1, I2C FLAG ADDR))4、还有个关于编程步骤的严谨性,跟STW想比,我们是先 Clcar ack,再 Clear Arrd。7.ADC采集1)ADC采样设置述ADC启动解决方法|分三个方面时写入后,需要等待一段时间,如果用库的话就在 ADC CMD后面加20us左右的延付如果采用中断获得采样数据后,需要软件清除中断。8. SDio1) SDIO DAT3pin的在1 bit bus mode和4 bit bus mode下的配置摧述1、SD|O在1 bit bus mode下,DAT3pin是低电平,这样会导致 SD Card进入SP!模式。原因:初始化失败的原因主要是因为GD32的芯片SDO的DAT3∏存在BUG2、在4位模式下,通过上面的方法,程序能止常初始化,但不能正常读写SD卡原因:因为DAT3∏在前面已经配置成推挽输出,所以在4位模式下,不危正常读下。在调用4位模式前,把DAT3的端凵配置成复用推挽输入即可解决问题解决方法「1、1 bit bus mode的解决方法:建议在使能之前,先把配置成推挽输出,)且要置成高电平,使保持高电平即可2、4 bit bus mode的解决方法:在调用4位模式前,把DAT3的端口配置成复用输出即可解决问题。2)程序在刚烧完后能正常读写SD卡,断电再上电后,SD卡初始化失败,需要手动复位一次后才正常描述在某些SD卡中,GD32断电再上电,会引起SD卡上的时钟信号不正常,导致SD卡发送命令失败。解决方法在程序中,打开时钟后,增加一小段延时,以保证下时钟信号稳定。这个延时添加的地方:在即的配置文件中,然后在这个函数中找到就在这个后面加个延时。10. USBA, USB OTG1)客户使用的原工程时需要注意几点解|1、在中,增加如下图红色字体语句for (1=0; 18; i++) EPli= GetEndPoiNT(i)for(i=0:iregs. HC REGS [num]->HCCHAR, hcchar d3 2)pdev->host hc Status =HC NAK而V2.1.0版本的NAK处理过程如下else if (hcint b nak)if(hcchar b. eptype = EP TYPE_ INTR)UNMASK HOST INT CHH(num)USB OTG HC Halt(pdev, numelse if ((hcchar. b. eptype = EP TYPE CTRL)(hcchar b eptype = EP_ TYPE BULK))A re-activate the channel *hcchar, b chen =1hcchar b chris =0USB OTG WRITE REG32(&pdev->regs. HC REGS [num]->HCCHAR, hcchar d32)pdey->host HC Status [num]=HC_NAKCLEAR HC INT(hcreg, nak)唯一的区别就是 CLEAR HC INT( here,nak)的位置,在Ⅵ1.0.0版本中对于CTRL和BUK端点的NAK中断没有清除NAK,我们的芯片会因此产生多次IN传输的请求,导致数据传输错误。改为V2.1.1的写法后传输正常。(注意 HC Status在V2.1.0是数组,在Ⅵ1.0.0是单个数据,直接拷贝的话要去掉后面的[num])B.USB外设的工作频率有限制摧述有最低工作频率的要求,也就是APB1分频后的时钟必须大于12MHz,比如HCLK为56MHz,APB1的最大分频系数为4,56/4=14MHz,可以正常工作。11 SPI1)输入与输出配置要求(STM32不需要如此要求)解决丨GD32在使用SP时,o的配置必须严格遵守主从模式下的输入与输出配置,而方法STM32无此要求,相关代码如下主机模式下|o配置(主机以SP为例):GPIO InitStructure gPio Mode gPio Mode af plGPIO_ Init Structure GPIo Speed GPlO Speed 50MHzGPIO InitStructure. GPio Pin= GPlO Pin 5 GPIO Pin_ 7;GPIO Init(GPIOA, &GPIO InitstructureGPio Init Structure gPio Mode gPio Mode IN floating:GPio InitStructure gpio Pin gpio pin 6GPIO Init(GPIOA, &GPIO InitStructure)从机模式下o配置(从机以SP2为例)GPIo Init Structure GPio Mode gPlo Mode IN FloatingGPIO InitStructure GPIO Speed= GPl Speed 50MHzGPIO_InitStructure GPIO_ Pin GPIO Pin_13 GPIO_ Pin_15GPIO Init(GPIOB, &GPIO InitStructure)gPio Initstructure gpio mode gpio mode af pp.GPIO InitStructure. GPio Pin= GPIo Pin 14:GPIO_Init(GPIOB, &GPIO_Initstructure);3)在GD32的SP的时钟信号,空闲状态需要配置成高电平,以保证数据的稳定性,具体代码如下:红色字体代码解决SPI_ InitStructure SPl Direction =SPI_ Direction_ 2Lines fullDuplex;方法SPI InitStructure SPl Mode SPi Mode master.SPI Initstructure SPl Data Size= SPl Data Size 8bSPlInitStructure SPl_CPOL= SPI CPOL HighSPl Initstructure SPl CPHA= SPI CPHA 2EdgeSPI InitStructure SPI NSS= SPI NSS SoftSPI InitStructure SPl BaudRate Prescaler =SPI Baud Rate Prescaler 256:SPI Initstructure, Spi FirstBit= SPI FirstBit MSBSPI InitStructure SPl CRCPolynomial =7;SPl Init(sPl1, &SPl Initstructure);4)当作为从机时,在GD32中,时钟信号必须为8的整数倍。例如:红色字体代码解决SPI_InitStructure SPl_ Direction =SPl_ Direction_ 2Lines_ Full Duplex;方法SPI InitStructure. SPl Mode= SPl Mode MasterSPI InitStructure SPSPi Data Size 8SPl InitStructure SPl CPOL= SPI CPOL High;SPI Init Structure. SPl CPHA SPI CPHA_ 2EdgeSPI Initstructure SPl NSS= SPI NSs SoftSPI Initstructure Spl BaudRatePrescaler= SPl BaudRatePrescaler 256SPI InitStructure. SPl FirstBit= SPl First Bit MSBSPl Initstructure SPl CRCPolynomial =7;SPI Init(SPI1, &SPl InitStructure)5)在GD32中,不能使用SPLS_FLAG_BSY该位来判断SP总线数据是否接收或发送完成12.看门狗1)进入SToP模式前打开看门狗,通过RTc的ALR唤醒后,程序会不断被复位的现像摧述WDG内部有个 Reload信号,KEY奇器写AAA会使其拉高,过段时间自动拉低。在拉底之前进入STOP状态会使 Reload信号一直为高,等到退出SToP后也保持为高,之后再写AAAA没有办法让 Reload产生上升沿,也就没办法更新计数器了解决方法「进STOP之前不要 Reload,也可以调整下程序的顺序,把WwDG的配置放到RIC配置之前,效果是一样的。
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Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. While the ieee administers the processand establishes rules to promote fairness in the consensus development process, the ieee does not independentlyevaluate, test, or verify the accuracy of any of the information contained in its standards.Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property orother damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly orindirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard documentThe ieee does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. IEEE Standardsdocuments are supplied "AS IsThe existence of an IEEE Standard does not imply that there are no other ways to produce, test, measurepurchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, theviewpoint expressed at the time a standard is approved and issued is subject to change brought about throughdevelopments in the state of the art and comments received from users of the standard Every IeeE Standard issubjected to review at least every five years for revision or reaffirmation. When a document is more than fiveyears old and has not been reaffirmed, it is reasonable to conclude Chat ils contents, although still of some valuedo not wholly reflect the present state of the art. Users are cautioned to check to determine that they have thelatest edition of any IEEE StandardIn publishing and making this document available, the IEeE is not suggesting or rendering professional or otherervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any dutyother person or entity to another. Any person utilizing this, and any other ieee Standards document, should relupon the advice of a competent professional in determining the exercise of reasonable care in any givencircumstancesInterpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiateaction to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. For thisreason, IEEE and the members of its societies and standards coordinating committees are not able to provide aninstant response to interpretation requests except in those cases where the matter has previously received formalconsideration. At lectures, symposia, seminars, or educational courses, an individual presenting information onIEee standards shall make it clear that his or her views should be considered the personal views of that individuarather than the formal position, explanation, or interpretation of the IeeeComments for revision of IEEE Standards are welcome from any interested party, regardless of membership aftil-iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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