FPGA应用开发入门与典型实例_源代码

【实例简介】通信信号调制制式的自动识别和调制参数的自动估计是非协作通信和软件 无线电中的主要问题。非协作通信是通信中的一个分支，在民用或军用场合都 有重要的应用，它需要接收机在先验知识不足的前提下监视空间通信信号的活 动情况，并截获其传输的信息内容；软件无线电是未来通信中的一个关键技术， 它需要接收机能在同一个硬件平台上自动完成多种体制、多个频段的通信和相 互间的切换。这里面都需要解决通信信号制式的自动识别和参数估计。另外， 信噪比（SNR）是接收信号的一个关键参数，它对通信系统的性能有着重要影响， 对它的估计也十分必要。直接扩频序列信号（DSSS）由于具有极低的功率谱密 度，如何在非协作通信中不知道扩频序列的前提下对其进行检测和估计，是一 个具有很强的应用背景同时富有挑战性的课题。本文以通信信号的统计特性为 基础，分别对这些问题进行了研究和探索，主要包括： 首先，使用统计模式识别的方法，综合决策树识别器和神经网络识别器的 优点，提出了一种混合识别器，它在不依赖于先验的调制参数和信噪比的条件 下能对常用的11种数字调制信号CW、BPSK、QPSK、OQPSK、16QAM，32QAM， 64QAM、2FSK、4FSK、GMSK和OFDM进行准确的识别。 其次，研究了非协作通信中观测信号调制参数的估计问题。对M-PSK及 M-QAM信号滚降系数的研究表明，接收机中滚降系数不准确对系统性能的影响 非常小，因此我们在设计接收机时可以不必考虑滚降系数的影响，而只需固定 一个值即可。对M-FSK号调制指数的研究表明，我们提出的估计算法能够显著 改善时钟同步性能，并且估计结果不影响最后的误码率。对M-PSK、M-QAM 及OQPSK信号波特率的研究表明，我们提出的波特率估计算法能够在较短的观 测长度下取得较高精度的波特率估计值，并且估计结果完全满足解调器所需的 精度要求。 再次，研究了观测信号SNR的估计问题，提出了两种不依赖于辅助数据的 估计算法，一种是改进的基于最小描述长度原理和特征值分解的算法，另一种 算法基于Gibbs抽样原理。这两种算法均能在AWGN信道和多径信道中精确估 计出信号的SNR。此外，第二种算法还可以给出信道的估计信息。 最后，利用扩频序列的强自相关特性和弱互相关特性，研究了DSSS信号在 非协作通信中的检测和参数估计问题。算法以接收信号自相关函数的累加为基计DSSS信号的波特率、chip速率和载波频率，然后提出了两个测度函数， 一个对扩频序列进行同步，确定出扩频序列在观测序列中正确的起始位置；另 一个在扩频序列同步的基础上估计序列中每一个chip的具体数值。计算机仿真 结果验证了理论分析的正确性。 本论文的研究结果表明：通过采用本论文提出的调制信号自动识别算法和 相关的调制参数估计算法，可以有效的提高非协作通信和软件无线电中接收机 的工作性能和实用化程度。

对熵值法实现了matlab的快速实现，使用者应该注意的是对数据的标准化处理有多样性，自己可以根据自己的情况合适修改相应的代码部分，本代码采用的是归一化处理，梅一列数据大小统一分布在【1,2】之间。

基于曼哈顿距离权重的Astar算法的单AGV路径规划（C#版),并对Astar算法的运行时间进行可视化显示。

我在青鸟学习时的几个考试上机项目,附有数据库,答案.正学java的朋友,一定来看看,好好练练.

涉及：QPSK信号调制（带噪声）、解调、加纳算法码元同步、科斯塔斯环载波同步。信号采样率32M 星座图显示 眼图显示

Matlab 官方有关于HDL coder开发的详细技术文档， HDL Coder可以把Simulink模型、MATLAB代码和Stateflow框图生成位真、周期精确、可综合的Verilog和VHDL代码，很适合用于FPGA/ASCI的快速开发，里面还有大量的例程等等ContentsHDL Code generation from MATLaBMATLAB Algorithm DesignData Types and scope1-2Supported data TUsuppyted data type1-3Scope for variables1-3Operators1-4Arithmetic operate1-4Relational operators1-4ogical Operators1-5Control flow statements1-6Vector Function Limitations related to Control1-7PersistentⅤ ariables1-8Persistent Array variables1-10Complex data Type Support1-11Declaring complex signaIs1-11Conversion Between Complex and real signals1-12Support for vectors of Complex Numb1-12ystem Objects1-14Why use System objects?1-14Predefined System Object1-14User-Defined System ob1-14Limitations of HDL Code Generation for SystemObjects1-15System object Examples for HDL Code Generation.. 1-16Predefined System Objects Supported for HDL CodeGeneration1-17Load constants from a mat-file1-18Generate Code for User-Defined System Objects1-19How To Create a User-Defined System object1-1User-Defined System object Example1-19Map Matrices to ROM1-22Fixed-Point bitwise Functions1-231-23Bitwise Functions Supported for HDl Code Generation 1-23Fixed-Point Run-Time Library functions1-29Fixed-Point function limitations1-33Model State with Persistent variables and SysteObjects1-34Bit Shifting and bit rotation1-8Bit Slicing and Bit Concatenation1-41Guidelines for Efficient hdL code1-43MATLAB Design Requirements for HDL CodeGeneration1-44What is a matlab test bench?1-45MATLAB Test Bench Requirements and bestractices1-46MATLAB Test Bench requirements1-46MATLAB Test bench best practices1-46ContentsMATLAB Best Practices and Design Patterns forHDL Code generation2Model a counter for hdl code generation2-2MATLAB Counter2-2MATLAB Code for the counter2-3Best Practices in this Example2-4Model a state machine for HDL Code Generation2-5MATLAB State machinesMATLAB Code for the Mealy State MachineMATLAB Code for the moore state machine2-7Best practic2-9Generate hardware Instances For local functions2-10MATLAB Local functions2-10MATLAB Code for mlhdlc two counters. m2-10Implement RAM USing MATLAB Code2-13Implementation of RAM2-13Implement RAM Using a Persistent Array or Systemobject Properties2-13Implement RAM Using hdl. RAM2-14For-Loop best Practices for HDL Code generation2-16MATLAB Loops2-16Monotonically Increasing Loop Counters2-16Persistent Variables in Loops2-17Persistent Arrays in Loops2-17Fixed-Point Conversion3Floating-Point to Fixed-Point Conversion3-2Fixed-Point Type Conversion and Refinement3-16Working with Generated Fixed-Point Files3-26Specify Type Proposal Options3-33Log Data for Histogram3-37Automated Fixed-Point Conversion3-40License Requirements3-40Automated Fixed-Point Conversion Capabilities3-40Code Coverage3-42Proposing Data Types3-45Locking Proposed Data Types3-47Viewing functions3-47lew1ariables3-48Istogram ...3-54Function Replacements3-56Validating Types3-57g Numerics3-57Detecting Overflows3-57Custom plot functions3-59Visualize Differences Between Floating-Point and Fixed-Point results3-61Inspecting Data Using the Simulation Data Inspector 3-67What Is the Simulation Data Inspecto3-67Import Logged Data3-67Export Logged data3-67Group signals3-67Run options3-68Create Report3-68Comparison Options3-68Enabling Plotting Using the Simulation Data Inspector 3-68Save and Load simulation Data Inspector Sessions3-68Enable Plotting Using the Simulation Data Inspector 3-70From the UI3-70From the Command Line3-70Replacing Functions Using Lookup TableApproximations·3-72Replace a custom function with a lookup Table3-73From the UI3-73i ContentsFrom the Command line3-81Replace the exp Function with a Lookup Table3-84From the ui3-84From the Command line3-92Data Type Issues in Generated Code3-94Enable the highlight Option in a MaTLAB CoderProject3-94Enable the Highlight Option at the Command Line... 3-94Stowaway doubles3-94Stowaway singles3-94Expensive Fixed-Point operations3-94Code GenerationCreate and set Up Your Project4-2Create a New Project4-2Open an Existing ProjectAdd Files to the project4-4Primary Function Input Specification4-6When to Specify Input Properties4-6Why You must Specify Input Properties4-6Properties to Specify4-6Rules for Specifying Properties of Primary Inputs4-8Methods for Defining Properties of Primary Inputs4-8Basic hdl code generation with the workflowAdvisor4-10HDL Code Generation from System Objects4-14Generate Instantiable code for functions4-19How to generate Instantiable Code for Functions4-19Generate Code Inline for Specific Functions4-19Limitations for instantiable code generation forFunctions4-19Integrate Custom HDL Code Into MATLAB Design.. 4-21Define the hdl. Black Box System object4-21Use System object In MATLAB Design Function4-23Generate HDL Code4-23limitations for hdl. black box4-26Enable matLab function block generation4-27Requirements for MaTLAB Function Block Generation 4-27Enable matlab function block generation4-27Results of matlab function block generation4-27System Design with HDL Code Generation fromMATLAB and simulink4-28Generate Xilinx System Generator Black Box Block4-32Requirements for System Generator Black Box BlockGeneration4-32Enable System Generator black Box block GeResults of System Generator Black Box Bloc neration4-32Generation4-33Generate Xilinx System Generator for DsP black boxfrom MATLAB HDL Design4-34Generate HDL Code from MATLAB Code Using theCommand line interface4-40Specify the Clock Enable rate4-45Why specify the clock Enable rate?4-45How to Specify the clock Enable rate4-45Specify Test Bench Clock Enable Toggle rate4-47When to Specify Test Bench Clock Enable Toggle rate4-47How to Specify Test Bench Clock Enable Toggle rate4-47Generate an HDL Coding Standard report fromMATLAB4-49Using the hdl Workflow advisor4-49Using the Command Line4-51Generate an HDL Lint Tool script4-53How To generate an hdl lint Tool Script4-53ContentsGenerate a Board-Independent Ip core from MATLAB 4-55Generate a board-Independent Ip core4-55Requirements and Limitations for IP Core generation4-57Minimize clock enables4-58Using the GUi4-59Using the Command Line4-59Limitations4-59VerificationVerify Code with HDL Test Bench5-2Generate Test bench with file i/oWhen to Use file i/o In Test bench5-5How Test bench generation with file i/o works5-5Test Bench Data files5-5How to generate Test bench with file i/o5-6Limitations When Using File 1/0 In Test Bench5-6DeploymentGenerate Synthesis Scripts6-2Optimization7RAM Mapping7-2Map persistent Arrays and dsp. Delay to RAM7-3How To Enable RaM Mapping7-3RAM Mapping requirements for Persistent Arrays andSystem object PropertiesRAM Mapping Requirements for dsp. Delay Systemob7-6RAM Mapping Comparison for MATLAB Code7-8Pipelining7-9Port registers7-9Input and Output Pipeline registers7-9Variable pipelining7-9Register Inputs and Outputs7-10Insert Input and Output Pipeline registers7-11Distributed Pipelining7-12What is Distributed Pipelin7-12Benefits and Costs of Distributed pipelining7-12Selected Bibliograph7-12Pipeline matlab variables7-13Using the hdl Workflow Advisor7-13Using the Command Line Interface7-13Limitations of MatlAB Variable Pipelining7-13Optimize MatLAb loops7-15oop Streaming7-15Loop unrolling7-15How to Optimize maTLaB loops7-15Limitations for MaTLAB Loop Optimization7-16Constant Multiplier optimization7-17Specify constant multiplier optimization7-19Distributed Pipelining for Clock Speed Optimization7-20Map Matrices to Block RAMs to Reduce Area7-27Resource Sharing of Multipliers to Reduce Area7-32Loop streaming to Reduce Area7-41Contents

最近公司需要实现 Android下（PDA）与公司设备（PLC）通讯和操作设备.(本人Android开发也是这个项目边学边做)，中间遇到了很多坑，也感谢CSDN上资源的共享。也看了不是Modbus4j.jar 实现ModbusTCP和PLC的小例子。。。总是云里雾里。现在结合项目抽取操作ＰＬＣ的代码贡献给这方便有需求的朋友。。。程序用到seroUtils.jar，modbus4J.jar。可以读写ＰＬＣ（１６位），同时也做了下浮点值的写入和处理。。朋友可以在此基础上进行变化。。。

光电信息技术，对水下光通信的研究水下光通信是一个新的研究热点，具有很好的现实价值

最佳小波包分解程序

【实例简介】对于做全局优化算法的研究人员是一本不可多得的测试函数大全